PCF8545ATTSLASHA datasheet(29/72 Pages) NXP

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PCF8545

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Product data sheet

Rev. 1 — 13 November 2013

29 of 72

NXP Semiconductors

PCF8545

Universal LCD driver for multiplex rates up to 1:8

8.6 Display register

The display register holds the display data while the corresponding multiplex signals are

generated.

8.7 Backplane outputs

The LCD drive section includes eight backplane outputs: BP0 to BP7. The backplane

output signals are generated based on the selected LCD multiplex drive mode.

• In 1:8 multiplex drive mode: BP0 to BP7 must be connected directly to the LCD.

• In 1:6 multiplex drive mode: BP0 to BP5 must be connected directly to the LCD.

• In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.

8.8 Segment outputs

The LCD drive section includes up to 44 segment outputs (S0 to S43) which must be

connected directly to the LCD. The segment output signals are generated based on the

multiplexed backplane signals and with data resident in the display register. When less

segment outputs are required, the unused segment outputs must be left open-circuit. The

number of available segments depends on the multiplex drive mode selected.

8.9 Display RAM

The display RAM stores the LCD data. Depending on the multiplex drive mode, the

arrangement of the RAM is changed.

• multiplex drive 1:8: RAM is 40  8 bit

• multiplex drive 1:6: RAM is 42  6 bit

• multiplex drive 1:4: RAM is 44  4 bit

Table 24.

Backplane and active segment combinations

Multiplex

drive mode

Active BPs

Active segments

1:8

BP0 to BP7

S0 to S39

1:6

BP0 to BP5

S0 to S41

1:4

BP0 to BP3

S0 to S43

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