PCF8545ATTSLASHA datasheet(51/72 Pages) NXP

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PCF8545

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Product data sheet

Rev. 1 — 13 November 2013

51 of 72

NXP Semiconductors

PCF8545

Universal LCD driver for multiplex rates up to 1:8

[1]

The minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either the SDA or SCL

is held LOW for a minimum of 25 ms. The bus time-out feature must be disabled for DC operation.

[2]

tVD;ACK = time for acknowledgement signal from SCL LOW to SDA output LOW.

[3]

tVD;DAT = minimum time for valid SDA output following SCL LOW.

[4]

Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.

Fig 42. RESET timing

Table 35.

Timing characteristics: I2C-bus

VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. All timing values are valid within the

operating supply voltage and temperature range and referenced to VIL and VIH with an input voltage swing of VSS to VDD.

Timing waveforms see Figure 43.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Pin SCL

fSCL

SCL clock frequency

[1] --

400

kHz

tLOW

LOW period of the SCL clock

1.3

s

tHIGH

HIGH period of the SCL clock

0.6

s

Pin SDA

tSU;DAT

data set-up time

100

tHD;DAT

data hold time

Pins SCL and SDA

tBUF

bus free time between a STOP

and START condition

1.3

s

tSU;STO

set-up time for STOP condition

0.6

s

tHD;STA

hold time (repeated) START

condition

0.6

s

tSU;STA

set-up time for a repeated START

condition

0.6

s

rise time of both SDA and SCL

signals

fSCL = 400 kHz

0.3

s

fSCL = 100 kHz

1.0

s

fall time of both SDA and SCL

signals

0.3

s

tVD;ACK

data valid acknowledge time

[2] 0.6

s

tVD;DAT

data valid time

[3] 0.6

s

capacitive load for each bus line

400

tSP

pulse width of spikes that must be

suppressed by the input filter

[4] --

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