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PCF8545ATT/A 数据表(PDF) 39 Page - NXP Semiconductors

部件名 PCF8545ATT/A
功能描述  Universal LCD driver for multiplex rates up to 1:8
PDF  72 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

PCF8545ATT/A 数据表(HTML) 39 Page - NXP Semiconductors

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PCF8545
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 13 November 2013
39 of 72
NXP Semiconductors
PCF8545
Universal LCD driver for multiplex rates up to 1:8
9.2.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
9.2.7 I2C-bus slave address
Device selection depends on the I2C-bus slave address. Two different I2C-bus slave
addresses can be used to address the PCF8545 (see Table 26).
The least significant bit of the slave address byte is bit R/W (see Table 27).
Bit 1 of the slave address is defined by connecting the input A0 to either VSS (logic 0) or
VDD (logic 1). Therefore, two instances of PCF8545 can be distinguished on the same
I2C-bus.
9.2.8 I2C-bus protocol
The I2C-bus protocol is shown in Figure 30. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of the two PCF8545 slave
addresses available. All PCF8545 with the corresponding A0 level acknowledge in
parallel to the slave address. But any PCF8545 with the alternative A0 level ignore the
whole I2C-bus transfer.
After acknowledgement, a control byte follows (see Section 9.1 on page 36).
The display bytes are stored in the display RAM at the address specified by the RAM data
pointer.
The acknowledgement after each byte is made only by the addressed PCF8545. After the
last data byte, the I2C-bus master issues a STOP condition (P). Alternatively a START
may be issued to RESTART an I2C-bus access.
Table 26.
I2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
0
MSB
LSB
011
100
A0
R/W
Table 27.
R/W-bit description
R/W
Description
0
write data
1
read data



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