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CB35000 数据表(PDF) 8 Page - STMicroelectronics |
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CB35000 数据表(HTML) 8 Page - STMicroelectronics |
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8 / 16 page  CB35000 SERIES 8/16 ® core scan cells are provided in the CB35000 Series library. Examples include FDxS/FJKxS cells which are edge sensitive and LSxx cells which are true LSSD cells. Non-overlapping clock generator macros are also available. EVALUATION DEVICE An evaluation device is used to demonstrate the performance of the CB35000 series as well as verify the effectiveness of the design system. The device has path delays, latches, a host of macrocells and memory functions which were Figure 5 Evaluation Device used to verify the simulated characteristics that are supplied in the data book. Characterization of the path delays including interconnect shows typical delays of 210 ps for a 2 input NAND with receivers/drivers operating at frequencies of 200 MHz. The evaluation device is available in a 208 pin plastic quad flat pack. |
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