CB35000 SERIES

6/16

®

Inside the slew rate sections the next slices of

specialized designed components step on a 50

micron wide pattern. The first of these 50 micron

wide sections is utilized for predriver circuits;

these include specialized built in test functions for

the I/O. The predriver of course interfaces the

core signals controlling tristate and switching

functions with the slew rate and output transistor

sections but it also allows all Output Buffers to be

driven high, low or put into tristate regardless of

the state of the internal logic greatly simplifying

parametric testing of the part and also assisting

customers who wish to use this feature during

board testing. Note that all output buffers can be

tristated by this function including buffers that

normally do not tristate. This test function also

turns off all pull up or down devices and shuts

down all differential receivers and converts them

into

standard

CMOS

receivers.

Inside

the

predriver is a section of specialized transistors

used to create the receiver functions. This

section

includes

specialized

non

salicide

protection resistor diodes to further protect the

gates of the receiver devices from ESD and latch

up. Also present in this section are devices that

can be utilized to form various parameteriseable

pull up, pull down and buskeeper functions. A full

set of standard receivers with pull up and pull

Table 4

Temperature (Junction) and Voltage

Multipliers

-55

0.77

-40

0.83

25

1.00

70

1.13

85

1.17

125

1.27

2.7

1.20

3.0

1.11

3.3

1.00

3.6

0.94

down devices is present in the library. The

technologies supported match the output buffer

capabilities and include, LVCMOS, LVTTL, GTL,

CTL, Differential, etc. and a five volt interface

capability.

All pads except the sixteen corner pads can be

configured as power or I/O pads. The configured

power pads are known as placeable pads and

have an associated current handling capability.

Their placement is dependent on the types of

output buffers used in the design. For rules

governing the placement of pads, please contact

your local SGS-THOMSON design centre.

CORE LOGIC

The propagation delays shown in the CB35000

data book are given for nominal processing, 3.3V

operation, and 25 C temperature conditions.

However there are additional factors that affect

the delay characteristics of the macrocells. These

include loading due to fanout and interconnect

routing, voltage supply, junction temperature of

the device, processing tolerance and input signal

transition time. Prior to physical layout, the

design

system

can

estimate

the

delays

associated with any critical path. The impact of

the placement and routing can be accurately RC

back

annotated

from

the

layout

for

final

simulations of critical timing. The effects of

Table 4. A third factor, is associated with process

variation. This multiplier has a minimum of 0.8

and a maximum of 1.2.

MACROCELLS AND MACROFUNCTIONS

The CB35000 series has internal macrocells that

are robust in variety and performance. The cell

selection has been driven by the need of

Synthesis and HDL based design techniques.

This

offering

is

rich

in

buffers,

complex

combinatorial cells and multi power drive cells,

which allow the Synthesis tool to create a netlist

compatible with the requirements of Place and

Route tools.

Macrofunctions are a series of soft-macros

facilitating quick capture of large functional blocks

and are available for such functions as counters,