CB35000 SERIES

4/16

®

LIBRARY

The following section details the elements which

make up the CB35000 Series library. The

elements are organized into three categories:

1. Macrocell

library

with

Input,

Output,

Bidirectional

Buffers

including

JTAG

macrocells and Core cells.

2. Macrofunctions

3. Module generators.

I/O BUFFERS

CB35000 technology does not utilize a standard

type I/O cell but is a leader in the emerging Sea

of I/O approach to handling the chip interface

problem. This approach starts at the bond pad

area of the I/O where the pad size and pitch is not

determined

until

the

customers

choice

of

packaging, signal interface standards and I/O

count is considered. Wire bond pad spacings for

80 micron centres are available where large

signal counts are most important.

Pad spacing can be increased incrementally. It is

expected that most designs will use 100 micron

spacings or above. It is also possible to use

different spacings for different width output

sections when needed within the same device.

Along with the variable bond pad spacing the I/O

output transistor section does not have a fixed

width. Previous technologies utilized a design

approach where the desired full function buffer

was designed for a maximum current taking one

pad location with the usual current in the range of

twenty four milliamps. The approach followed in

CB35000 is to have identical twenty five micron

wide output transistor slices stepped around the

die. Each slice contains one set of protection

diodes to the external power rails and eight P and

eight

N

transistors.

The

transistors

are

specifically laid out and selectively non salicided

for ESD protection and latch up prevention.

These slices are paralleled to meet the current

needs of the user, for example, to construct a

24mA sink and 12mA source LVTTL buffer, a

number of slices would be used. The next group

of devices that makes up the I/O circuits is again

a 25u wide slice of specialized transistors that are

utilized to form the slew rate control sections of

the I/O. Each of these slices has circuits to

control the switching of up two sections of P and

N output transistors. These sections are of

course created from the output transistor slice

above the slew rate section and can be

connected as desired by the designer. Many

configurations of circuits can be created to supply

the desired results with slew rate slices paralleled

with multiple output sections. A further function of

the I/O circuits is current spike suppression

during switching of the I/O transistors. The logic

utilized causes the conducting transistors to turn

off before the opposing set of transistors turn on.

Figure 3

IO Buffer Technology

INPUT

CONTROL

SLEW RATE

TRISTATE

BUSKEEPER

LEVEL SHIFTER

PROGRAMMABLE

PITCH BOND PADS

DIE CORE

GUARDRING

EDGE OF DIE

SEGMENTED

OUTPUT

RIVER OF DRIVE

TRANSISTORS

4mA

Selected