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L9301 数据表(PDF) 48 Page - STMicroelectronics |
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L9301 数据表(HTML) 48 Page - STMicroelectronics |
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48 / 54 page ![]() SPI L9301 48/54 DS11400 Rev 9 13.5 SPI timings Figure 13. SPI timing diagram 3 9 5 7 8 6 2 MSB OUT 4 15 13 14 10 LSB IN DATA DATA LSB OUT MSB IN 1 GAPG0809150846PS Table 30. SPI timing characteristics No Symbol Parameter Conditions Min Max Units 1 fop Transfer frequency Design Information - 6 MHz 2 tsclk SCLK period Design Information 167 - ns 3 tlead Enable lead time Design Information 750 - ns 4 tlag Enable lag time Design Information 100 - ns 5 tsclkhs SCLK high time Design Information 75 - ns 6 tsclkls SCLK low time Design Information 75 - ns 7 tsus MOSI input setup time Design Information 30 - ns 8 ths MOSI input hold time Design Information 30 - ns 9 ta MISO access time 50 pF load - 100 ns 10 tdis MISO disable time 50 pF load - 100 ns 11 tvs MISO output valid time 50 pF load - 70 ns 12 tho MISO output hold time 50 pF load 10 - ns 13 tr MISO rise time 50 pF load - 50 ns 14 tf MISO fall time 50 pF load - 50 ns 15 tcsn CS negated time Design Information 750 - ns 16 tsh SCLK Hold Time Design Information 100 - ns |
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