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L9663 数据表(PDF) 83 Page - STMicroelectronics |
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L9663 数据表(HTML) 83 Page - STMicroelectronics |
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83 / 106 page  DS11401 Rev 6 83/106 L9663 Communication interface 105 MISO This output signal is used to transfer data serially out of the device. Data is shifted out on the rising edge of Serial Clock (SCLK). MISO is in high impedance under POR condition. 5.2.2 Clock and data characteristics A microcontroller with its SPI peripheral running in the following mode can drive the SPI: CPOL = '0' and CPHA = '1'. The communication frame starts with the falling edge of the CS (Communication Start). SCLK has to be low. The MOSI data are then latched on all following falling SCLK edges into the internal shift registers. After Communication Start, the MISO will leave tri-state and shift the MSB of the output data on MISO. On all following rising SCLK edges data are shifted out through the internal shift registers to MISO. The communication frame is finished with the rising edge of CS. If a valid communication took place (e.g. correct number of SCLK cycles), the operation requested will be performed (Write or Clear operation). |
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