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L9663 数据表(PDF) 95 Page - STMicroelectronics |
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L9663 数据表(HTML) 95 Page - STMicroelectronics |
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95 / 106 page  DS11401 Rev 6 95/106 L9663 Electrical characteristics 105 Table 21. Synchronous pulse amplitude monitoring Symbol Parameter / Condition Min Typ Max Unit VAsync_l Sync pulse amplitude under voltage monitoring threshold (if VT2_SYNCx_SEL bit is set to 0) (1) 1. The sync pulse amplitude and the diagnostic threshold voltage level are referred to the inputs of the difference amplifier, i.e. VAsync = V(PSIx-VAS). 2.4 - 2.8 V VAsyncU Sync pulse amplitude under voltage monitoring threshold (if VT2_SYNCx_SEL bit is set to 1) 3.5 - 3.85 V tAsync_V Filter time for insufficient sync pulse amplitude - 2 - µs Table 22. Time slot monitoring Symbol Parameter / Condition Min Typ Max Unit tTSM Resolution of the time slots - 1 - µs Required register size for each time slot - 12 - bit Table 23. Digital I/O Symbol Parameter / Condition Min Typ Max Unit Vin_High Input high threshold - - 2 V Vin_Low Input low threshold 0.8 - - V Vin_HYS Hysteresis 100 150 - mV Iin_pu Input pull up current (pins CS, MOSI, SCLK) -30 -45 -60 µA Iin_pd Input pull down current (pins SYNC1, SYNC2, CLKIN) 30 45 60 µA Vout_High Output high level (Isource = 2 mA) VDD-0.4 - VDD V Vout_Low Output low level (Isink = 2 mA) - - 0.4 V Table 24. Frequency references Symbol Parameter / Condition Min Typ Max Unit fCLK Internal oscillator frequency (FLL disabled) 15.2 16 16.8 MHz fCLK Internal oscillator frequency (FLL enabled, normal CLKIN frequency) 15.84 16 16.16 MHz fCLKIN-normal Normal CLKIN input frequency (1MHz or 4MHz) (Test info) -0.5% 1 / 4 +0.5% MHz tT_CKMSK FLL Mask time - - 16 ms tT_CKERD Clock error detection time (if FLL is enabled and CLKIN is stuck) - - 260 µs treaction Clock error reaction time (if bit REACTTIME=1) -20- ms |
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