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L9924L 数据表(PDF) 69 Page - STMicroelectronics |
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L9924L 数据表(HTML) 69 Page - STMicroelectronics |
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69 / 84 page ![]() DocID028840 Rev 3 69/84 L9924L SPI interface 83 The bits of this register are write only (WO) and their value isn’t latched: any successive read attempt returns 0. A write access to a locked bit must be preceded by the relevant unlock operation: if a read/write access to any other register is done the unlock condition is lost and a write access to a locked bit will have no effect. 12.4.11 SYSTEM OPERATION register [0x02] By writing this register it is possible to configure the system behavior related to watchdog and reset. The configuration bits are locked and any write access must be preceded by an unlock operation. Table 52. SYSTEM OPERATION register [0x02] Bit Register name Reset value Description 13 Reserved - 12 SEL24V_EN (LOCKED) 0 Set this bit to configure 24V support. This option is possible only if the relevant OTP bit is set 11 Reserved - 10 Reserved - 9 WDG_INIT_ENABLE (LOCKED) 0/1(1) 1. On power on reset the value of these bit is 0, on wakeup the bits maintain the last programmed values (if any); these bits are not cleared by the SW reset command. Write 1 to disable the initial 500 ms watchdog timeout 8 WDG_FAIL_REST_uC (LOCKED) 0/1(1) When 0 a watchdog failure can only switch the power stage off, when 1 a watchdog failure switches the power stage off and resets the microcontroller 7-5 Reserved - 4 Apply EPONA Cfg-REGs SW Reset (LOCKED) 0(2) 2. After a SW reset the Watchdog is also initialized and, if not previously disabled, must be programmed and refreshed to avoid a watchdog error occurrence. Write 1 to force a default condition (SW RESET) corresponding to the reset status. This command doesn't clear the content of bits 8 and 9 and doesn't clear the content of read and read and clear bits. 3-1 Reserved - 0 POWER_OFF (LOCKED)(3) 3. The POWER_OFF command is ignored if at least one, among the enabled wake-up sources (see register 0x04) is active. It's up to the application SW ti implement the appropriate power off sequence 0 Writing 1 the system enters standby mode if no key input is active. |
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