L9924L datasheet(77/84 Pages) STMICROELECTRONICS

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L9924L

SPI interface

12.4.19

WATCHDOG REFRESH register [0x0F]

This register must be suitably written to refresh the watchdog; it also contains the current

watchdog counter value.

12.5

SPI sequence example

This paragraph shows a simple Smart Power command sequence for a system in the

following conditions:



L-key active



5 ms square wave input applied to phase input



Watchdog disabled (test mode)

Table 60. WATCHDOG REFRESH register [0x0F]

Bit

Reset value

Description

13-10 Reserved

9-8

WDG_Refr_CODE

Watchdog refresh code:

– 00: not valid

– 01: word A (first refresh word to send to the device)

–10: word B

– 11: not valid

Words A and B must be sent alternatively

7-0

WDG_Timer

0 (RO)

Watchdog current counter value. The resolution is

specified by bits 13 and 12 of watchdog config register.

The counter is cleared on watchdog error occurrence.

These bits are read only: any write attempt will have no

effect

Table 61. SPI sequence examples

Operation

MOSI

MISO

Comment

Read and Clear wakeup

source register (0x11)

4440A5 060A20

GSW:

– CP-LOW (charge pump not yet activated)

– Key active

DATA

– L-KEY (key status)

– VDD-UV

– WKUP_BY_L (wake up source)

Read and Clear general

status register (0x12)

4840A5 060100

GSW:

– CP-LOW (charge pump not yet activated)

– Key active

DATA: CP-LOW

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