INA745AIRELR datasheet(23/50 Pages) TI2

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6.5.1.2 High-Speed I2C Mode

When the bus is idle, both the SDA and SCL lines are pulled high by the pullup resistors. The controller

generates a start condition followed by a valid serial byte containing high-speed (HS) controller code 00001XXX.

This transmission is made in fast (400kHz) or standard (100kHz) (F/S) mode at no more than 400kHz. The

INA745x does not acknowledge the HS controller code, but the INA745x does recognize the code and switches

the internal filters to support 2.94MHz operation.

The controller then generates a repeated start condition (a repeated start condition has the same timing as

the start condition). After this repeated start condition, the protocol is the same as F/S mode, except that

transmission speeds up to 2.94MHz are allowed. Instead of using a stop condition, use repeated start conditions

to maintain the bus in HS-mode. A stop condition ends the HS-mode and switches all the internal filters of the

device to support the F/S mode.

6.5.1.3 SMBus Alert Response

The INA745x is designed to respond to the SMBus Alert Response address. The SMBus Alert Response

provides a quick fault identification for simple targets. When an Alert occurs, the controller can broadcast the

Alert Response target address (0001 100) with the Read/Write bit set high. Following this Alert Response, any

target that generates an alert acknowledges the Alert Response and sending the address on the bus.

The Alert Response can activate several different targets simultaneously, similar to the I2C General Call. If

more than one target attempts to respond, bus arbitration rules apply. The losing device does not generate an

Acknowledge and continues to hold the Alert line low until that device wins arbitration.

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INA745A, INA745B

SBOSAC3B – JULY 2023 – REVISED AUGUST 2025

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INA745AIRELR 数据表(PDF) 23 Page - Texas Instruments