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INA745AIRELR 数据表(PDF) 29 Page - Texas Instruments |
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INA745AIRELR 数据表(HTML) 29 Page - Texas Instruments |
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29 / 50 page  Table 7-11. DIAG_ALRT Register Field Descriptions (continued) Bit Field Type Reset Description 9 MATHOF R 0h This bit is set to 1 if an arithmetic operation resulted in an overflow error. This bit indicates that current and power data can be invalid. 0h = Normal 1h = Overflow Must be manually cleared by triggering another conversion or by clearing the accumulators with the RSTACC bit. 8 RESERVED R 0h Reserved. Always read 0. 7 TMPOL R 0h This bit is set to 1 if the temperature measurement exceeds the threshold limit in the temperature over-limit register. 0h = Normal 1h = Overtemperature Event When ALATCH =1 this bit is cleared by reading or writing to this register. 6 CURRENTOL R 0h This bit is set to 1 if the current measurement exceeds the threshold limit in the current over-limit register. 0h = Normal 1h = Overcurrent Event When ALATCH =1 this bit is cleared by reading or writing to this register. 5 CURRENTUL R 0h This bit is set to 1 if the current measurement falls below the threshold limit in the current under-limit register. 0h = Normal 1h = Undercurrent Event When ALATCH =1 this bit is cleared by reading or writing to this register. 4 BUSOL R 0h This bit is set to 1 if the bus voltage measurement exceeds the threshold limit in the bus over-limit register. 0h = Normal 1h = Bus Over-Limit Event When ALATCH =1 this bit is cleared by reading or writing to this register. 3 BUSUL R 0h This bit is set to 1 if the bus voltage measurement falls below the threshold limit in the bus under-limit register. 0h = Normal 1h = Bus Under-Limit Event When ALATCH =1 this bit is cleared by reading or writing to this register. 2 POL R 0h This bit is set to 1 if the power measurement exceeds the threshold limit in the power limit register. 0h = Normal 1h = Power Over-Limit Event When ALATCH =1 this bit is cleared by reading or writing to this register. 1 CNVRF R 0h This bit is set to 1 if the conversion is completed. 0h = Normal 1h = Conversion is complete When ALATCH =1 this bit is cleared by reading or writing to this register or starting a new triggered conversion. 0 MEMSTAT R 1h This bit is set to 0 if a checksum error is detected in the device trim memory space. 0h = Memory Checksum Error 1h = Normal Operation www.ti.com INA745A, INA745B SBOSAC3B – JULY 2023 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: INA745A INA745B |
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