5.16 Switching Characteristics—3.3V Supply

VCC1 = VCC2 = 3.3V ±10% (over recommended operating conditions unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tPLH, tPHL

Propagation delay time

See Figure 6-1

6

10.8

16

ns

PWD

Pulse width distortion(1) |tPHL – tPLH|

0.7

4.2

ns

tsk(o)

Channel-to-channel output skew time(2)

Same-direction channels

2.2

ns

tsk(pp)

Part-to-part skew time

4.5

ns

tr

Output signal rise time

See Figure 6-1

0.8

3

ns

tf

Output signal fall time

0.8

3

ns

tPHZ

Disable propagation delay, high-to-high impedance

output

See Figure 6-2

17

32

ns

tPLZ

Disable propagation delay, low-to-high impedance

output

17

32

ns

tPZH

Enable propagation delay, high impedance-to-high

output for ISO7842

17

32

ns

Enable propagation delay, high impedance-to-high

output for ISO7842F

2

2.5

μs

tPZL

Enable propagation delay, high impedance-to-low

output for ISO7842

2

2.5

μs

Enable propagation delay, high impedance-to-low

output for ISO7842F

17

32

ns

tfs

Default output delay time from input power loss

Measured from the time VCC goes below 1.7V. See

Figure 6-3

0.2

9

μs

tie

Time interval error

216 – 1 PRBS data at 100Mbps

0.91

ns

(1)

Also known as Pulse Skew.

(2)

tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same

direction while driving identical loads.

ISO7842, ISO7842F

SLLSEJ0I – OCTOBER 2014 – REVISED JULY 2025

www.ti.com

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