EF9345 datasheet(2/38 Pages) STMICROELECTRONICS

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PIN DESCRIPTION (All the input/output pins are TTL compatible)

Name

Type

Pin N

Function

Description

MICROPROCESSOR INTERFACE

AD(0:7)

I/O

17-29

21-25

Multiplexed

Address/Data

Bus

These 8 bidirectional pins provide communication with the

microprocessor system bus.

Address

Strobe

The falling edge of this control signal latches the address on the

AD(0:7) lines, the state of the Data Strobe (DS) and Chip Select (CS)

into the chip.

Data Strobe

When this input is strobed high by AS, the output buffers are selected

while DS is low for a read cycle (R/W = 1).

In write cycle, data present on AD(0:7) lines are strobed by R/W low

(see timing diagram 2).

When this input is strobed low by AS, R/W gives the direction of data

transfer on AD(0:7) bus. DS high strobes the data to be written during

a write cycle (R/W = 0) or enables the output buffers during a read

cycle (R/W = 1). (see timing diagram 1).

R/W

Read/Write

This input determines whether the Internal registers get written or

read. A write is active low (”O”).

Chip Select

The EF9345 is selected when this input is strobed low by AS.

MEMORY INTERFACE

ADM(0:7)

I/O

40-43

Multiplexed

Address/Data

Bus

Lower 8 bits of memory address appear on the bus when ASM is

high. It then becomes the data bus when ASM is low.

AM(8:13)

32-27

Memory

Address Bus

These 6 pins provide the high order bits of the memory address.

Output Enable

When low, this output selects the memory data output buffers.

Write Enable

This output determines whether the memory gets read or written. A

write is active low (”0”).

ASM

Memory

Address

Strobe

This signal cycles continuously. Address can be latched on its falling

edge.

OTHER PINS

CLK

Clock Input

External TTL clock Input (nominal value : 12MHz, duty cycle : 50%).

VSS

Power Supply

Ground.

VCC

Power Supply

+5V

VIDEO INTERFACE

Red

Green

Blue

These outputs deliver the video signal. They are low during the

vertical and horizontal blanking intervals.

Insert

This active high output allows to insert R : G: B : in an external video

signal for captioning purposes, for example. It can also be used as a

general purpose attribute or color.

HVS/HS

Sync. Out

This output delivers either the composite synchro (bit TGS4 = 1) or the

horizontal synchro signal (bit TGS4 =0)

PC/VS

Phase

Comparator /

Vertical Sync

When TGS4 = 1, this signal is the phase comparator output.

When TGS4 = 0, this output delivers the vertical synchro signal.

SYNC IN

Synchro In

This input allows vertical and/or horizontal synchronizing the EF9345

on an external signal. It must be grounded if not used.

Video Clock

This output delivers a 4MHz clock phased with the R, G, B, I signals.

EF9345

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