EF9345 datasheet(6/38 Pages) STMICROELECTRONICS

6 / 38 page

MICROPROCESSOR INTERFACE

EF9345 is motel compatible. It automatically se-

lects the processor type by using AS input latch to

state of the DS input.

No external logic is needed to adapt bus control

signals from most of the common multiplexed bus

microprocessors.

EF9345

6801

INTEL Family

Timing 1

Timing 2

ALE

DS, E,

φ 2

R/W

MICROPROCESSOR INTERFACE TIMING AD(0:7), AS, DS, R/W, CS

VCC = 5.0V

±5%, TA = 0 to + 70°C, CL = 100pF on AD(0:7)

Reference Levels : VIL = 0.8V and VIH = 2V on All Inputs ; VOL = 0.4V and VOH on all Outputs.

Symbol

Ident. N

Parameter

Min.

Typ.

Max.

Unit

tCYC

Memory Cycle Time

400

tASD

DS Low to AS High (Timing 1)

DS High or R/W High to AS High (Timing 2)

tASED

AS Low to High (Timing 1)

AS Low to DS Low or R/W Low (Timing 2)

tPWEH

Write Pulse Width

200

tPWASH

AS Pulse Width

100

tRWS

R/W to DS Setup Time (Timing 1)

100

tRWH

R/W to DS Hold Time (Timing 1)

tASL

Address and CS Setup Time

tAHL

Address and CS Hold Time

tDSW

Data Setup Time (Write Cycle)

100

tDHW

Data Hold Time (Write Cycle)

tDDR

Data Access Time from DS (Read Cycle)

150

tDHR

DS Inactive to High Impedance State Time (Read Cycle)

tACC

Address to Data Valid Access Time

300

INPUT DATA

OUTPUT

DATA

ADDRESS

ASM

R/W

WRITE CYCLE

AD (0:7)

READ CYCLE

AD (0:7)

Figure 3 : Microprocessor Interface Timing Diagram 1 (6801 Type)

EF9345

6/38

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