EF9345 datasheet(5/38 Pages) STMICROELECTRONICS

5 / 38 page

MEMORY INTERFACE

VCC = 5.0V

±5%, TA = 0 to + 70°C

Clock : fin = 12MHz ; Duty Cycle 40 to 60% ; tr,tf < 5ns

Reference Levels : VIL = 0.8V and VIH =2V, VOL = 0.4V and VOH = 2.4V

Symbol

Ident. N

Parameter

Min.

Typ.

Max.

Unit

tELEL

Memory Cycle Time

500

Output Delay Time from CLK Rising Edge (ASM, OE, WE)

tEHEL

ASM High Pule Width

120

tELDV

Memory Access Time from ASM Low

290

tDA

Output Delay Time from CLK Rising Edge (ADM(0:7), AM(8:13))

tAVEL

Address Setup Time to ASM

tELAX

Address Hold Time from ASM

tCLAZ

Address Off Time

tGHDX

Memory Hold Time

tOZ

Data Off Time from OE

tGLDV

Memory OE Access Time

150

tQVWL

Data Setup Time (Write Cycle)

tWHQX

Data Hold Time (Write Cycle)

tWLWH

WE Pulse Width

110

C L

Test

Point

R L

MMD7000

or equivalent

Figure 1 : Test Load

Table 1

Symbol

AM(8:13)

ADM(0:7)

AD(0:7)

Other

Outputs

100pF

50pF

Ω

3.3k

Ω

4.7k

Ω

4.7k

Ω

READ ADDRESS

WRITE ADDRESS

D IN

D OUT

CLK

ASM

ADM (0:7)

AM (8:14)

Figure 2 : Memory Interface Timing Diagram

EF9345

5/38

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