M41ST87YMX6F datasheet(37/54 Pages) STMICROELECTRONICS

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M41ST87W

Clock operation

DocID9497 Rev 11

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Table 11: Reset AC characteristics

Symbol

Parameter

(1)

Min

Max

Unit

tR1

(2)

RSTIN1lowtoRSTlow(minpulsewidth)

100

200

tR2

(2)

RSTIN2lowtoRSTIN2high(minpulsewidth)

100

200

trec

(3)

RSTIN1orRSTIN2hightoRSThigh

(3)

Notes:

(1)

Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V (except where

noted).

(2)

Pulse widths of less than 100 ns will result in no RESET (for noise immunity).

(3)

Programmable (see

Table 13: "trec definitions"). Same function as power-on reset.

3.10

Power-fail comparators (1 and 2)

Two power-fail inputs (PFI1 and PFI2) are compared to an internal reference voltage (1.25

V). If either PFI1 or PFI2 is less than the power-fail threshold (VPFI), the associated power-

fail output (

PFO

1 or

PFO

2) will go low. This function is intended for use as an under-voltage

detector to signal a failing power supply. Typically PFI1 and PFI2 are connected through

external voltage dividers (see Figure 5: "Hardware hookup") to either the unregulated DC

input (if it is available) or the regulated output of the VCC regulator. The voltage divider can

be set up such that the voltage at PFI1 or PFI2 falls below VPFI several milliseconds before

the regulated VCC input to the M41ST87Y/W or the microprocessor drops below the

minimum operating voltage, thus providing an early warning of power failure.

During battery back-up, the power-fail comparator turns off and

PFO

1 and

PFO

2 go (or

remain) low. This occurs after VCC drops below VPFD(min). When power returns,

PFO

1 and

PFO

2 are forced high, irrespective of VPFI for the write protect time (trec), which is the time

from VPFD(max) until the inputs are recognized. At the end of this time, the power-fail

comparator is enabled and

PFO

1 and

PFO

2 follow PFI1 and PFI2. If the comparator is

unused, PFI1 or PFI2 should be connected to VSS and the associated

PFO

1 or

PFO

2 left

unconnected.

3.11

Power-fail outputs

The

PFO

1 and

PFO

2 outputs are programmable as N-channel, open drain output drivers, or

full-CMOS output drivers. By setting the power-fail output open drain bit (PFOD) to a '1,' the

output will be configured as open drain (with IOL as specified in Table 19: "DC

characteristics"). When PFOD is set to '0,' the outputs will be configured as full-CMOS (sink

and source current as specified in Table 19: "DC characteristics").

Note: When configured as open drain (PFOD = '1'),

PFO

1 and

PFO

2 will require an external

pull-up resistor.

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