ICS843002I-41

700MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR

IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR

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ICS843002AKI-41 REV. A OCTOBER 25, 2007

Schematic Example

Figure 7 shows a schematic example of the ICS843002I-41

application schematic. In this example, the device is operated at

VCC = 3.3V. The decoupling capacitors should be located as close

as possible to the power pin. The input is driven by a 3.3V LVPECL

driver. The 2-pole filter example is used in this schematic. Please

refer to the ICS843002I-41 datasheet for additional loop filter

recommendations.

Figure 7. ICS843002I-41 Schematic Example

Loss of Reference Indicator (LOR0 and LOR1) Output Pins

The LOR0 and LOR1 pins are controlled by the internal clock

activity monitor circuits. The clock activity monitor circuits are

clocked by the VCXO PLL phase detector feedback clock. The

LOR output is asserted high if there are three consecutive

feedback clock edges without any reference clock edges (in both

cases, either a negative or positive transition is counted as an

“edge”). The LOR output will otherwise be low. In a phase detector

observation interval, the activity monitor does not flag excessive

reference transitions as an error. The monitor only distinguishes

between transitions occurring and no transitions occurring.