ICS843002I-41

700MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR

IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR

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ICS843002AKI-41 REV. A OCTOBER 25, 2007

Power Supply Filtering Technique

As in any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter

performance, power supply isolation is required. The

ICS843002I-41 provides separate power supplies to isolate any

connected to the power supply plane through vias, and 0.01µF

bypass capacitors should be used for each pin. Figure 1 illustrates

an additional 10

Ω resistor along with a 10µF bypass capacitor be

Figure 1. Power Supply Filtering

Wiring the Differential Input to Accept Single Ended Levels

Figure 2 shows how the differential input can be wired to accept

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio of

R1 and R2 might need to be adjusted to position the V_REF in the

center of the input voltage swing. For example, if the input clock

R2/R1 = 0.609.

Figure 2. Single-Ended Signal Driving Differential Input

3.3V

10

Ω

10µF

.01µF

.01µF

V_REF

Single Ended Clock Input

CLKx

nCLKx

R1

1K

C1

0.1u

R2

1K