ICS843002I-41

700MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR

IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR

7

ICS843002AKI-41 REV. A OCTOBER 25, 2007

NOTE 1: Outputs terminated with 50

Ω to V

diagram.

NOTE 1: Outputs terminated with 50

Test Circuit diagram.

AC Electrical Characteristics

See Parameter Measurement Information section.

NOTE 1: Defined as skew between outputs at the same supply voltage, same frequency, and with equal load conditions.

Measured at the output differential cross points.

NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 3: Please refer to the Phase Noise plots.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Output High Voltage; NOTE 1

V

Output Low Voltage; NOTE 1

V

Peak-to-Peak Output Voltage Swing

0.6

1.0

V

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Output High Voltage; NOTE 1

V

Output Low Voltage; NOTE 1

V

Peak-to-Peak Output Voltage Swing

0.4

1.0

V

Parameter

Symbol

Test Conditions

Minimum

Typical

Maximum

Units

Output Frequency

19.44

700

MHz

tsk(o)

Output Skew; NOTE 1, 2

50

ps

tjit(Ø)

RMS Phase Jitter (Random);

NOTE 3

155.52MHz,

Integration Range: 12kHz – 20MHz

0.81

ps

Output Rise/Fall Time

20% to 80%

100

800

ps

odc

Output Duty Cycle

45

55

%