SONET/SDH JITTER ATTENUATOR

ICS843002I-41

IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR

1

ICS843002AKI-41 REV. A OCTOBER 25, 2007

General Description

The ICS843002I-41 is a member of the

HiperClockS™ family of high performance clock

solutions from IDT. The ICS843002I-41 is a PLL

based synchronous clock generator that is

optimized for SONET/SDH line card applications

where jitter attenuation and frequency translation is needed. The

device contains two internal PLL stages that are cascaded in

series. The first PLL stage uses a VCXO which is optimized to

provide reference clock jitter attenuation and to be jitter tolerant,

and to provide a stable reference clock for the 2nd PLL stage

(typically 19.44MHz). The second PLL stage provides additional

frequency multiplication (x32), and it maintains low output jitter by

using a low phase noise FemtoClock™VCO. PLL multiplication

ratios are selected from internal lookup tables using device input

selection pins. The device performance and the PLL multiplication

ratios are optimized to support non-FEC (non-Forward Error

Correction) SONET/SDH applications with rates up to OC-48

(SONET) or STM-16 (SDH). The VCXO requires the use of an

external, inexpensive pullable crystal. VCXO PLL uses external

passive loop filter components which are used to optimize the PLL

loop bandwidth and damping characteristics for the given

line card application.

The ICS843002I-41 includes two clock input ports. Each one can

accept either a single-ended or differential input. Each input port

also includes an activity detector circuit, which reports input clock

activity through the LOR0 and LOR1 logic output pins. The two

input ports feed an input selection mux. “Hitless switching” is

accomplished through proper filter tuning. Jitter transfer and

wander characteristics are influenced by loop filter tuning, and

phase transient performance is influenced by both loop filter

tuning and alignment error between the two reference clocks.

Typical ICS843002I-41 configuration in SONET/SDH Systems:

19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz,

622.08MHz

19.44MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz,

Hi-Z

Features

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or

single-ended LVCMOS or LVTTL levels

(12kHz to 20MHz): 0.81ps (typical)

packages

Pin Assignment

ICS843002I-41

32-Lead VFQFN

5mm x 5mm x 0.925mm package body

K Package

Top View

HiPerClockS™

ICS

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

LF1

LF0

ISET

CLK0

nCLK0

CLK_SEL

QA_SEL2

LOR0

LOR1

nc

nQB

QB