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IS25LE01G-RILA3-TY 数据表(PDF) 31 Page - Integrated Silicon Solution, Inc

部件名 IS25LE01G-RILA3-TY
功能描述  SERIAL FLASH MEMORY 133/104MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC
PDF  186 Pages
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制造商  ISSI [Integrated Silicon Solution, Inc]
网页  http://www.issi.com
标志 ISSI - Integrated Silicon Solution, Inc

IS25LE01G-RILA3-TY 数据表(HTML) 31 Page - Integrated Silicon Solution, Inc

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IS25LE01G
IS25WE01G
Integrated Silicon Solution, Inc.- www.issi.com
31
Rev. A6
01/14/2025
1.8V Device (IS25WE)
P[6:3]
Dummy
Cycles2,3
Fast Read5
0Bh/0Ch
Fast Read5
0Bh/0Ch
Fast Read
Dual
Output
3Bh/3Ch
Fast Read
Dual IO
BBh/BCh
Fast Read
Quad
Output
6Bh/6Ch
Fast Read
Quad IO
EBh/ECh
FRDTR
0Dh/0Eh
FRDDTR
BDh/BEh
FRQDTR
EDh/EEh
SPI
QPI
SPI
SPI
SPI
SPI, QPI
SPI/QPI
SPI4
SPI, QPI
0
Default1
104MHz
75MHz
104MHz
84MHz
104MHz
75MHz
60/60MHz
60MHz
60MHz
1
1
66MHz
25MHz
66MHz
33MHz
50MHz
25MHz
50/11MHz
29MHz
11MHz
2
2
84MHz
33MHz
84MHz
50MHz
66MHz
33MHz
60/23MHz
40MHz
23MHz
3
3
104MHz
40MHz
104MHz
66MHz
75MHz
40MHz
60/34MHz
52MHz
34MHz
4
4
104MHz
50MHz
104MHz
84MHz
84MHz
50MHz
60/46MHz
60MHz
46MHz
5
5
104MHz
66MHz
104MHz
90MHz
95MHz
66MHz
60/58MHz
60MHz
58MHz
6
6
104MHz
75MHz
104MHz
104MHz
104MHz
75MHz
60/60MHz
60MHz
60MHz
7
7
104MHz
84MHz
104MHz
104MHz
104MHz
84MHz
60/60MHz
60MHz
60MHz
8
8
104MHz
93MHz
104MHz
104MHz
104MHz
93MHz
60/60MHz
60MHz
60MHz
9
9
104MHz
104MHz
104MHz
104MHz
104MHz
104MHz
60/60MHz
60MHz
60MHz
10
10
104MHz
104MHz
104MHz
104MHz
104MHz
104MHz
60/60MHz
60MHz
60MHz
11
11
104MHz
104MHz
104MHz
104MHz
104MHz
104MHz
60/60MHz
60MHz
60MHz
12
12
104MHz
104MHz
104MHz
104MHz
104MHz
104MHz
60/60MHz
60MHz
60MHz
13
13
104MHz
104MHz
104MHz
104MHz
104MHz
104MHz
60/60MHz
60MHz
60MHz
14
14
104MHz
104MHz
104MHz
104MHz
104MHz
104MHz
60/60MHz
60MHz
60MHz
15
15
104MHz
104MHz
104MHz
104MHz
104MHz
104MHz
60/60MHz
60MHz
60MHz
Notes:
1. Default dummy cycles are as follows.
Operation
Command
Dummy Cycles
Comment
SPI mode
QPI mode
SPI mode
QPI mode
Fast Read
0Bh/0Ch
0Bh/0Ch
8
6
RDUID, IRRD instructions are also
applied.
Fast Read Dual Output
3Bh/3Ch
-
8
-
Fast Read Quad Output
6Bh/6Ch
-
8
-
Fast Read Dual IO
BBh/BCh
-
4
-
Fast Read Quad IO
EBh/ECh
EBh/ECh
6
6
Fast Read DTR
0Dh/0Eh
0Dh/0Eh
8
6
Fast Read Dual IO DTR
BDh/BEh
-
4
-
Fast Read Quad IO DTR
EDh/EEh
EDh/EEh
6
6
2. Enough number of dummy cycles must be applied to execute properly the AX read operation.
3. Must satisfy bus I/O contention. For instance, if the number of dummy cycles and AX bits cycles are same, then X
must be Hi-Z.
4. QPI mode is not available for FRDDTR command.
5. RDUID, IRRD instructions are also applied.



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