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IS25LE01G-RILA3-TY 数据表(PDF) 40 Page - Integrated Silicon Solution, Inc |
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IS25LE01G-RILA3-TY 数据表(HTML) 40 Page - Integrated Silicon Solution, Inc |
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40 / 186 page  IS25LE01G IS25WE01G Integrated Silicon Solution, Inc.- www.issi.com 40 Rev. A6 01/14/2025 7. PROTECTION MODE The device supports hardware and software write-protection mechanisms. 7.1 HARDWARE WRITE PROTECTION The Write Protection (WP#) pin provides a hardware write protection method for BP3, BP2, BP1, BP0, SRWD, and QE in the Status Register. Refer to the section 6.1 STATUS REGISTER. Write inhibit voltage (VWI) is specified in the section 9.8 POWER-UP AND POWER-DOWN. All write sequence will be ignored when Vcc drops to VWI. Table 7.1 Hardware Write Protection on Status Register SRWD WP# Status Register 0 Low Writable 1 Low Protected 0 High Writable 1 High Writable Note: Before the execution of any program, erase or Write Status/Function Register instruction, the Write Enable Latch (WEL) bit must be enabled by executing a Write Enable (WREN) instruction. If the WEL bit is not enabled, the program, erase or write register instruction will be ignored. 7.2 SOFTWARE WRITE PROTECTION The device also provides two kinds of software write protection feature. One is Block Protection by Block Protection bits (BP3, BP2, BP1, BP0) and another is Advanced Sector/Block Protection (ASP). When Block Protection is enabled (i.e., any BP3- 0 are set to “1”), Advanced Sector/Block Protection (ASP) can still be used to protect sectors/blocks not protected by the Block Protection scheme. In the case that both ASP and Block Protection are used on the same sector/block the logical OR of ASP and Block Protection related to the sector/block is used. Warning: ASP and Block Protection should not be used concurrently. Use one or the other, but not both. 7.2.1 BLOCK PROTECTION BITS The device provides a software write protection feature. The Block Protection bits (BP3, BP2, BP1, BP0) allow part or the whole memory area to be write-protected. For details, see 6.1 Status Register. |
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