IS25LE01G-RILA3-TY datasheet(49/186 Pages) ISSI

49 / 186 page

IS25LE01G

IS25WE01G

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A6

01/14/2025

8. DEVICE OPERATION

8.1 COMMAND OVERVIEW

The device utilizes an 8-bit instruction register. Refer to Table 8.4. Instruction Set for details on instructions and

instruction codes. All instructions, addresses, and data are shifted in with the most significant bit (MSB) first on

Serial Data Input (SI) or Serial Data IOs (IO0, IO1, IO2, IO3). The input data on SI or IOs is latched on the rising

edge of Serial Clock (SCK) for normal mode and both of rising and falling edges for DTR mode after Chip Enable

(CE#) is driven low (VIL). Every instruction sequence starts with a one-byte instruction code and is followed by

address bytes and/or dummy cycles (configurable) and/or data bytes, depending on the type of instruction. CE#

must be driven high (VIH) after the last bit of the instruction sequence has been shifted in to end the operation.

Commands are structured as follows:

• Each command begins with a byte (eight bits) instruction.

• The instruction may be stand alone or may be followed by address bits to select a location within one of several

address spaces in the device. The address may be either a 24-bit or 32-bit byte boundary address.

• The SPI interface with Multiple IO provides the option for each transfer of address and data information to be

done one, two, or four bits in parallel. This enables a tradeoff between the number of signal connections (IO bus

width) and the speed of information transfer. If the host system can support a two or four bit wide IO bus the

memory performance can be increased by using the instructions that provide parallel two bit (dual) or parallel

four bit (quad) transfers.

• The width of all transfers following the instruction are determined by the instruction sent.

• All single bit or parallel bit groups are transferred in most to least significant bit order.

• Some instructions send Mode Bits following the address to indicate that the next command will be of the same

type with an implied, rather than an explicit, instruction. The next command thus does not provide an instruction

byte, only a new address and mode bits. This reduces the time needed to send each command when the same

command type is repeated in a sequence of commands.

• The address or Mode Bits may be followed by Dummy Cycles before read data is returned to the host.

• Dummy Cycles may be zero to several SCK cycles. In fact, Mode Bits will be counted as a part of Dummy

Cycles.

• All instruction, address, Mode, and data information is transferred in byte granularity. Addresses are shifted into

the device with the Most Significant Byte first. All data is transferred with the lowest address byte sent first.

Following bytes of data are sent in lowest to highest byte address order i.e. the byte address increments.

• All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations)

are ignored. The embedded operation will continue to execute without any affect. A very limited set of commands

are accepted during an embedded operation. These are discussed in the individual command descriptions.

While a program, erase, or write operation is in progress, it is recommended to check that the Write In Progress

(WIP) bit is

“0” before issuing most commands to the device, to ensure the new command can be accepted.

• Depending on the command, the time for execution varies. A command to read status information from an

executing command is available to determine when the command completes execution and whether the

command was successful.

• Following are some general signal relationship descriptions to keep in mind.

– The host always controls the Chip Enable (CE#), Serial Clock (SCK), and Serial Input (SI) - SI for single bit

wide transfers. The memory drives Serial Output (SO) for single bit read transfers. The host and memory

alternately drive the IO0-IO3 signals during Dual and Quad transfers.

– All commands begin with the host selecting the memory by driving CE# low before the first rising edge of

SCK. CE# is kept low throughout a command and when CE# is returned high the command ends.

Generally, CE# remains low for 8-bit transfer multiples to transfer byte granularity information. All commands

will not be accepted if CE# is returned high not at an 8-bit boundary.

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