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IS25LE01G-RILA3 数据表(PDF) 80 Page - Integrated Silicon Solution, Inc |
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IS25LE01G-RILA3 数据表(HTML) 80 Page - Integrated Silicon Solution, Inc |
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80 / 186 page ![]() IS25LE01G IS25WE01G Integrated Silicon Solution, Inc.- www.issi.com 80 Rev. A6 01/14/2025 Figure 8.17 Fast Read Quad I/O AX Read Sequence (EBh [EXTADD=0], 3-byte address) 20 CE # SCK 4 0 4 0 3-byte Address 16 12 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 3 Mode 0 IO0 IO1 21 5 1 5 1 17 13 9 22 6 2 6 2 18 14 10 23 7 3 7 3 19 15 11 Mode Bits IO2 IO3 5 1 4 0 5 1 4 0 6 2 6 2 7 3 7 3 ... ... ... ... Data Out 1 Data Out 2 ... tV 6 Dummy Cycles Notes: 1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When the mode bits are different from AXh, the device exits the AX read operation. 2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles. 3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles are same, then X should be Hi-Z. |
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