IS25LE01G-RILA3 datasheet(129/186 Pages) ISSI

129 / 186 page

IS25LE01G

IS25WE01G

Integrated Silicon Solution, Inc.- www.issi.com

129

Rev. A6

01/14/2025

8.43 FAST READ DUAL IO DTR MODE OPERATION (FRDDTR, BDh or 4FRDDTR, BEh)

The FRDDTR/4FRDDTR instruction enables Double Transfer Rate throughput on dual I/O of the device in read

mode. The address (interleave on dual I/O pins) is latched on both rising and falling edge of SCK, and the data

(interleave on dual I/O pins) shift out on both rising and falling edge of SCK at a maximum frequency fT2. The 4-bit

address can be latched-in at one clock, and 4-bit data can be read out at one clock, which means two bits at the

rising edge of clock, the other two bits at the falling edge of clock.

The first address byte can be at any location. The address is automatically increased to the next higher address

after each byte of data is shifted out, so the whole memory can be read out with a single FRDDTR/4FRDDTR

instruction. The address counter rolls over to 0 when the highest address is reached. Once writing

FRDDTR/4FRDDTR instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-

bit.

• BDh (EXTADD=0) is followed by a 3-byte address (A23-A0) or

• BDh (EXTADD=1) is followed by a 4-byte address (A31-A0) or

• BEh is followed by a 4-byte address (A31-A0)

The sequence of issuing FRDDTR/4FRDDTR instruction is: CE# goes low → Sending FRDDTR/4FRDDTR

instruction (1-bit per clock) → 24-bit or 32-bit address interleave on IO1 & IO0 (4-bit per clock) as above → 4 dummy

clocks (configurable, default is 4 clocks) on IO1 & IO0 → Data out interleave on IO1 & IO0 (4-bit per clock) → End

FRDDTR/4FRDDTR operation via pulling CE# high at any time during data out (Please refer to Figures 8.86 and

8.87 for 2 x I/O Double Transfer Rate Read Mode Timing Waveform).

If AXh (where X is don’t care) is input for the mode bits during dummy cycles, the device will enter AX read operation

mode which enables subsequent FRDDTR/4FRDDTR execution skips command code. It saves cycles as

described in Figures 8.88 and 8.89.

When the code is different from AXh (where X is don’t care), the device exits

the AX read operation. After finishing the read operation, device becomes ready to receive a new command.

If the FRDDTR/4FRDDTR instruction is issued while an Erase, Program or Write cycle is in process is in progress

(WIP=1), the instruction will be rejected without any effect on the current cycle.

IS25LE01G-RILA3 数据表(PDF) 129 Page - Integrated Silicon Solution, Inc