IS25LE01G-RILA3 datasheet(138/186 Pages) ISSI

138 / 186 page

IS25LE01G

IS25WE01G

Integrated Silicon Solution, Inc.- www.issi.com

138

Rev. A6

01/14/2025

FAST READ QUAD IO DTR MODE OPERATION IN QPI MODE (FRQDTR, EDh OR 4FRQDTR, EEh)

The FRQDTR/4FRQDTR instruction in QPI mode utilizes all four IO lines to input the instruction code so that only

two clocks are required, while the FRQDTR/4FRQDTR instruction in SPI mode requires that the byte-long

instruction code is shifted into the device only via IO0 line in eight clocks. As a result, 6 command cycles will be

reduced by the FRQDTR/4FRQDTR instruction in QPI mode. In addition, subsequent address and data out are

shifted in/out via all four IO lines like the FRQDTR/4FRQDTR instruction. In fact, except for the command cycle,

the FRQDTR/4FRQDTR operation in QPI mode is exactly same as the FRQDTR/4FRQDTR operation in SPI mode.

It is not required to set QE bit

to “1”.before Fast Read Quad I/O DTR instruction in QPI mode.

• EDh (EXTADD=0) is followed by a 3-byte address (A23-A0) or

• EDh (EXTADD=1) is followed by a 4-byte address (A31-A0) or

• EEh is followed by a 4-byte address (A31-A0)

The sequence of issuing FRQDTR/4FRQDTR instruction is: CE# goes low → Sending FRQDTR/4FRQDTR

instruction (4-bit per clock) → 24-bit or 32-bit address interleave on IO3, IO2, IO1 & IO0 (8-bit per clock) as above

→ 6 dummy clocks (configurable, default is 6 clocks) → Data out interleave on IO3, IO2, IO1 & IO0 (8-bit per clock)

→ End FRQDTR/4FRQDTR operation by driving CE# high at any time during data out.

If AXh (where X is don’t care) is input for the mode bits during dummy cycles, the device will enter AX read operation

mode which enables subsequent FRQDTR/4FRQDTR in QPI mode execution skips command code. It saves cycles

as described in Figures 8.92 and 8.93.

When the code is different from AXh (where X is don’t care), the device

exits the AX read operation. After finishing the read operation, device becomes ready to receive a new command.

If the FRQDTR/4FRQDTR instruction in QPI mode is issued while an Erase, Program or Write cycle is in process

is in progress (WIP=1), the instruction will be rejected without any effect on the current cycle.

IS25LE01G-RILA3 数据表(PDF) 138 Page - Integrated Silicon Solution, Inc