IMS C011

/30

18

&

Interrupt

Enable

Output

Ready

OutputInt

7

6

5

4

3

210

Figure 6.4

IMS C011 Mode 2 output status register

6.6

OutputInt

The OutputInt output is set high to indicate that the link is free to receive data from the microprocessor

for transmission as a data packet out of the serial link. It is inhibited from going high when the

interrupt

enable bit in the output status register is low (section 6.4.4). OutputInt is reset low when data is written

to the data output register; it is set low by Reset (page 7).

6.7

Data read

A data packet received on the input link sets the

data present flag in the input status register. If the interrupt

enable bit in the status register is set, the InputInt output pin will be set high. The microprocessor will either

respond to the interrupt (if the

interrupt enable bit is set) or will periodically read the input status register

until the

data present bit is high.

When data is available from the link, the microprocessor reads the data packet from the data input register.

This will reset the

data present flag and cause the link adaptor to transmit an acknowledge packet out of

the serial link output. InputInt is automatically reset by reading the data input register; it is not necessary

to read or write the input status register.

6.8

Data write

When the data output buffer is empty and a link acknowledge has been received the

output ready flag in

the output status register is set high. If the

interrupt enable bit in the status register is set, the OutputInt

output pin will also be set high. The microprocessor will either respond to the interrupt (if the

interrupt en-

able bit is set) or will periodically read the output status register until the output ready bit is high.

When the

output ready flag is high, the microprocessor can write data to the data output buffer. This will

result in the link adaptor resetting the

output ready flag and commencing transmission of the data packet

out of the serial link. The

output ready status bit will remain low until the data byte transmission has been

completed and an acknowledge packet is received by the input link. This will set the

output ready flag high;

if the

interrupt enable bit is set, OutputInt will also be set high.