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CLC030 数据表(PDF) 7 Page - National Semiconductor (TI) |
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CLC030 数据表(HTML) 7 Page - National Semiconductor (TI) |
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7 / 29 page ![]() AC Electrical Characteristics (Continued) Note 8: Average value measured between rising edges computed over at least one video field. Note 9: Intrinsic timing jitter is measured in accordance with SMPTE RP 184-1996, SMPTE RP 192-1996 and the applicable serial data transmission standard, SMPTE 259M-1997 or SMPTE 292M (proposed). A color bar test pattern is used. The value of fSCLK is 270 MHz or 360 MHz for SMPTE 259M, 540MHz for SMPTE 344M or 1,485 MHz for SMPTE 292M serial data rates. See Timing Jitter Bandpass section. Note 10: Intrinsic jitter is defined in accordance with SMPTE RP 184-1996 as: jitter at an equipment output in the absence of input jitter. As applied to this device, the input port is VCLK and the output port is SDO or SDO. Test Loads 20000304 Timing Jitter Bandpass 20000306 www.national.com 7 |
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