CLC030 datasheet(11/29 Pages) NSC

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Device Operation (Continued)

CONTROL DATA WRITE FUNCTIONS

Figure 2 shows the sequence of clock and control signals for

writing control data to the ancillary/control data port. The

control data write mode is similar to the read mode. The

control data write mode is started by making both the ANC/

CTRL input low and the RD/WR input low. Next, the 8-bit

address of the control register set to be accessed is placed

on port bits AD[7:0]. When a control register write address is

being written to the port, AD[9:8] must be driven as 00b

(0XXh, where XX are AD[7:0]). Toggle ACLK. The address is

captured on the rising edge of ACLK. Remove the address

after clocking it into the device on or before the falling edge

of ACLK. Observe the port input hold timing specification.

Next, the control register data is placed on the AD[7:0] port.

ACLK is again toggled. The data is written to the selected

being written to the port, AD[9:8] must be driven as 11b

(3XXh, where XX are AD[7:0]). Remove the register data

after clocking it into the device on or before the falling edge

of ACLK. Observe the port input hold timing specification.

Example: Setup (without enabling) the TPG Mode via the

AD port using the 1125 line, 30 frame, 74.25MHz, interlaced

component (SMPTE 274M) color bars as test pattern. The

TPG may be enabled after setup using the Multi-function I/O

port or by the control registers.

Set ANC/CTRL to a logic-low.

Set RD/WR to a logic-low.

Present 00Dh to AD[9:0] as the Test 0 register address.

Toggle ACLK.

Present 327h to AD[9:0] as the register data.

Toggle ACLK.

ANCILLARY DATA FUNCTIONS

The CLC030 can multiplex Ancillary Data into the serial

component video data stream. The ancillary data packet

structure, formatting and control words are given in standard

SMPTE 291M. The data may reside in portions of the hori-

zontal and vertical blanking intervals. The data can consist of

different types of message packets including audio data. The

CLC030 supports ancillary data in the HANC and VANC

areas of standard definition component video and in the

chrominance channel (C’r/C’b) only for high-definition opera-

tion. As it applies to embedded (multiplexed) audio data, this

function follows the recommended practice for AES/EBU

default Level A data handling.

Figure 3 shows the sequence of clock, data and control

signals for writing Ancillary Data to the port. In ancillary data

write mode, 10-bit ancillary data is written into the AD[9:0]

port and subsequently into the ancillary data FIFO. From the

FIFO, the ancillary data can be inserted into the ancillary

data areas in the serial video data stream. Ancillary data may

be written to the FIFO only when in the ancillary data mode.

Ancillary data cannot be read from the FIFO through the AD

Port.

The process of loading ancillary data into the FIFO is done

during the active video portion of the video line. Occurrence

of the active video line interval is indicated by the H-bit in the

fourth word of the TRS sequence. The H-bit is available on

I/O Port bit-2.

The ancillary data write process begins by making the ANC/

CTRL input high and the RD/WR input low. Next, the data

words are presented to the port in sequence as specified in

SMPTE 291M beginning with the DID word. Data presented

to the port within the required setup and hold time param-

eters will be written into the FIFO on the rising edge of

ACLK. The user has the option of including a checksum in

the ANC input data or of having the CLC030 calculate and

append the checksum. The CLC030 will append the Ancillary

Data Flag to each packet automatically before multiplexing

with the video data.

The process of writing ancillary data to the FIFO is effectively

a double-buffered write operation. Therefore, in order to

properly write the last word of the data packet, the CRC,

whether supplied with the ANC data packet or internally

generated, to the FIFO, ACLK must be toggled two addi-

tional times after the last data word is clocked into the port

(or when the CRC is being generated internally and ap-

pended). In the case where multiple packets are being

loaded to the FIFO, the additional clocks are issued after the

last word of the final packet is received by the port.

20000310

FIGURE 2. Control Data Write Timing

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