BAT to GND...........................................................-0.3V to +60V

ISET to BAT..........................................................-2.0V to +0.3V

IN1, IN2 to GND ................ -3V to lower of +60V or (VBAT + 1V)

AOUT1, DOUT1, AOUT2, DOUT2,

SLEEP

to GND....................................................-0.3V to +6V

Short-Circuit Duration

AOUT1, DOUT1, AOUT2, DOUT2 to GND

or to 5.5V (individually)........................................Continuous

Current In to IN1, IN2.....................................................±100mA

Current In to Any Other Pin..............................................±20mA

Continuous Power Dissipation for a Single-Layer Board

(TA = +70ºC)

10-Pin μMAX (derate 5.6mW/ºC) above +70ºC .......444.4mW

Continuous Power Dissipation for a Multilayer Board

(TA = +70ºC)

10-Pin μMAX (derate 8.9mW/ºC) above +70ºC .......715.6mW

Operating Temperature Range..........................-40ºC to +125ºC

Junction Temperature......................................................+150ºC

Storage Temperature Range.............................-65ºC to +160ºC

Lead Temperature (soldering, 10s) .................................+300ºC

Soldering Temperature (reflow).......................................+260ºC

PACKAGE TYPE: 10 µMAX

Package Code

U10+2

Outline Number

21-0061

Land Pattern Number

90-0330

THERMAL RESISTANCE, FOUR-LAYER BOARD:

Junction to Ambient (θJA)

112°C/W

Junction to Case (θJC)

37°C/W

MAX9621

Dual, 2-Wire Hall-Effect Sensor Interface

with Analog and Digital Outputs

www.maximintegrated.com

Maxim Integrated │ 2

Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Package Information

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.

For detailed information on package thermal considerations, refer to

www.maximintegrated.com/thermal-tutorial.

For the latest package outline information and land patterns (footprints), go to

www.maximintegrated.com/packages. Note that a “+”,

“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing

pertains to the package regardless of RoHS status.