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L6917B

Digital to Analog Converter

The built-in digital to analog converter allows the adjustment of the output voltage from 1.100V to 1.850V with

25mV as shown in the previous table 1. The internal reference is trimmed to ensure the precision of 0.8% and

a zero temperature coefficient around 70°C. The internal reference voltage for the regulation is programmed by

the voltage identification (VID) pins. These are TTL compatible inputs of an internal DAC that is realized by

means of a series of resistors providing a partition of the internal voltage reference. The VID code drives a mul-

tiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an amplifier ob-

taining the VPROG voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are provided

(realized with a 5

µA current generator up to 3.3V max); in this way, to program a logic "1" it is enough to leave

the pin floating, while to program a logic "0" it is enough to short the pin to GND. VID code “11111” programs

the NOCPU state: all mosfets are turned OFF and the condition is latched.

The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the over-

voltage protection (OVP) thresholds.

Soft Start and INHIBIT

At start-up a ramp is generated increasing the loop reference from 0V to the final value programmed by VID in

2048 clock periods as shown in figure 2.

to discharge the output capacitor and to protect the load from high side mosfet failures. Once soft start begins,

the reference is increased; when it reaches the bottom of the oscillator triangular waveform (1V typ) also the

upper MOS begins to switch and the output voltage starts to increase with closed loop regulation.. At the end of

the digital soft start, the Power Good comparator is enabled and the PGOOD signal is then driven high (See fig.

2). The Under Voltage comparator enabled when the reference voltage reaches 0.8V.

ing normal operation, if any under-voltage is detected on one of the two supplies the device shuts down.

Forcing the OSC/INH/FAULT pin to a voltage lower than 0.8V the device enter in INHIBIT mode: all the power

mosfets are turned off until this condition is removed. When this pin is freed, the OSC/INH/FAULT pin reaches

the band-gap voltage and the soft start begins.

Figure 2. Soft Start

PGOOD

t

t

t

t

2V

Turn ON threshold

2048 Clock Cycles

Timing Diagram

Acquisition: