L6917B

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Driver Section

The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the

RDSON), maintaining fast switching transition.

The drivers for the high-side mosfets use BOOTx pins for supply and PHASEx pins for return. The drivers for

the low-side mosfets use VCCDRV pin for supply and PGND pin for return. A minimum voltage of 4.6V at VC-

CDRV pin is required to start operations of the device.

The controller embodies a sophisticated anti-shoot-through system to minimize low side body diode conduction

time maintaining good efficiency saving the use of Schottky diodes. The dead time is reduced to few nanosec-

onds assuring that high-side and low-side mosfets are never switched on simultaneously: when the high-side

mosfet turns off, the voltage on its source begins to fall; when the voltage reaches 2V, the low-side mosfet gate

drive is applied with 30ns delay. When the low-side mosfet turns off, the voltage at LGATEx pin is sensed. When

it drops below 1V, the high-side mosfet gate drive is applied with a delay of 30ns. If the current flowing in the

inductor is negative, the source of high-side mosfet will never drop. To allow the turning on of the low-side mos-

fet even in this case, a watchdog controller is enabled: if the source of the high-side mosfet don't drop for more

than 240ns, the low side mosfet is switched on so allowing the negative current of the inductor to recirculate.

This mechanism allows the system to regulate even if the current is negative.

The BOOTx and VCCDR pins are separated from IC's power supply (VCC pin) as well as signal ground (SGND

pin) and power ground (PGND pin) in order to maximize the switching noise immunity. The separated supply

for the different drivers gives high flexibility in mosfet choice, allowing the use of logic-level mosfet. Several com-

bination of supply can be chosen to optimize performance and efficiency of the application. Power conversion

is also flexible, 5V or 12V bus can be chosen freely.

The peak current is shown for both the upper and the lower driver of the two phases in figure 3. A 10nF capac-

itive load has been used. For the upper drivers, the source current is 1.9A while the sink current is 1.5A with

VCCDR = 12V.

Figure 3. Drivers peak current: High Side (left) and Low Side (right)

Current Reading and Over Current

by the external resistor Rg placed outside the chip between ISENx and PGNDSx pins toward the reading points.

The full differential current reading rejects noise and allows to place sensing element in different locations with-

out affecting the measurement's accuracy. The current reading circuitry reads the current during the time in

CH3 = HGATE1; CH4 = HGATE2

CH3 = LGATE1; CH4 = LGATE2