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pins to the load in order to compensate losses along the output power traces and also to avoid the pick-up of

any common mode noise. Connecting these pins in points far from the load will cause a non-optimum load reg-

ulation, increasing output tolerance.

Current Reading: The Rg resistor has to be placed as close as possible to the ISENx and PGNDSx pins in

order to limit the noise injection into the device. The PCB traces connecting these resistors to the reading point

must be routed as parallel traces in order to avoid the pick-up of any common mode noise. It's also important

to avoid any offset in the measurement and to get a better precision, to connect the traces as close as possible

to the sensing elements, dedicated current sense resistor or low side mosfet Rdson.

Moreover, when using the low side mosfet RdsON as current sense element, the ISENx pin is practically con-

nected to the PHASEx pin. DO NOT CONNECT THE PINS TOGETHER AND THEN TO THE HS SOURCE!

The device won't work properly because of the noise generated by the return of the high side driver. In this case

route two separate nets: connect the PHASEx pin to the HS Source (route together with HGATEx) with a wide

net (30 mils) and the ISENx pin to the LS Drain (route together with PGNDSx). Moreover, the PGNDSx pin is

always connected, through the Rg resistor, to the PGND: DO NOT CONNECT DIRECTLY TO THE PGND! In

this case, the device won't work properly. Route anyway to the LS mosfet source (together with ISENx net).

Right and wrong connections are reported in Figure 15.

Symmetrical layout is also suggested to avoid any unbalance between the two phases of the converter.

Figure 15. PCB layout connections for sense nets

APPLICATION EXAMPLES

The dual-pahse topology can be applied to several different applications ranging from CPU power supply (for

which the device has been designed) to standard high current DC-DC power supply. The application benefits

of all the advantages due to the dual-phase topology ranging from output ripple reduction to dynamic perfor-

mance increase. After a general demo board overview, the following application examples will be illustrated:

Demo Board Description

The demo board shows the operation of the device in a dual phase application. This evaluation board allows

output voltage adjustability (1.100V - 1.850V) through the switches S0-S4 and high output current capability.

The board has been laid out with the possibility to use up to two D

to give maximum flexibility in the mosfet's choice.

The four layers demo board's copper thickness is of 70

µm in order to minimize conduction losses considering

the high current that the circuit is able to deliver.

Demo board schematic circuit is reported in Figure 16.

Wrong (left) and correct (right) connections for the current reading sensing nets.

NOT CORRECT

CORRECT

To PHASE

connection

VIA to GND plane

To HS Gate

and Source

To LS Drain

and Source