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as well as for the voltage spikes generated by the distributed inductance along the copper traces are so mini-

mized.

In fact, the further the mosfet is from the device, the longer is the interconnecting gate trace and as a conse-

quence, the higher are the voltage spikes corresponding to the gate pwm rising and falling signals. Even if these

spikes are clamped by inherent internal diodes, propagation delays, noise and potential causes of instabilities

are introduced jeopardizing good system behavior. One important consequence is that the switching losses for

the high side mosfet are significantly increased.

For this reason, it is suggested to have the device oriented with the driver side towards the mosfets and the

GATEx and PHASEx traces walking together toward the high side mosfet in order to minimize distance (see fig

14). In addition, since the PHASEx pin is the return path for the high side driver, this pin must be connected

directly to the High Side mosfet Source pin to have a proper driving for this mosfet. For the LS mosfets, the re-

turn path is the PGND pin: it can be connected directly to the power ground plane (if implemented) or in the

same way to the LS mosfets Source pin. GATEx and PHASEx connections (and also PGND when no power

ground plane is implemented) must also be designed to handle current peaks in excess of 2A (30 mils wide is

suggested).

Gate resistors of few ohms help in reducing the power dissipated by the IC without compromising the system

efficiency.

Figure 14. Device orientation (left) and sense nets routing (right)

The placement of other components is also important:

– The bootstrap capacitor must be placed as close as possible to the BOOTx and PHASEx pins to mini-

mize the loop that is created.

– Decoupling capacitor from Vcc and SGND placed as close as possible to the involved pins.

– Decoupling capacitor from VCCDR and PGND placed as close as possible to those pins. This capacitor

sustains the peak currents requested by the low-side mosfet drivers.

– Refer to SGND all the sensible components such as frequency set-up resistor (when present) and also

the optional resistor from FB to GND used to give the positive droop effect.

– Connect SGND to PGND on the load side (output capacitor) to avoid undesirable load regulation effect

and to ensure the right precision to the regulation when the remote sense buffer is not used.

– An additional 100nF ceramic capacitor is suggested to place near HS mosfet drain. This helps in reduc-

ing noise.

– PHASE pin spikes. Since the HS mosfet switches in hard mode, heavy voltage spikes can be observed

on the PHASE pins. If these voltage spikes overcome the max breakdown voltage of the pin, the device

can absorb energy and it can cause damages. The voltage spikes must be limited by proper layout, the

use of gate resistors, Schottky diodes in parallel to the low side mosfets and/or snubber network on the

low side mosfets, to a value lower than 26V, for 20nSec, at Fosc of 600kHz max.

s

Current Sense Connections.

Remote Buffer: The input connections for this component must be routed as parallel nets from the FBG/FBR

Towards HS mosfet

(30 mils wide)

Towards LS mosfet

(30 mils wide)

Towards HS mosfet

(30 mils wide)

To LS mosfet

(or sense resistor)

To regulated output

To LS mosfet

(or sense resistor)