13/46

L7250

1.2 Default serial port timing Table

1.3 Inverted clock comunication modes (bit 7, Reg05H) = 1

To set the bit7, Reg05H to 1, entering this different comunication mode, a writing process using the default co-

munication protocol (see the above paragraph) must be used.

After the SEN falling edge, the internal state machine is waiting for the first SCLK rising edge. This means that

if the SCLK line starts from a low level the first rising edge, respecting the setup time Tefcr, is considered, and

is used to read the R/W bit. The internal state machine must see 16 SCLK rising edges to validate the write

operation. The write mode is started if the R/W bit is low on the first rising edge of SCLK. The read mode is

started if the R/W bit is high on the first rising edge of SCLK. The ID, Address, and Data are all then subsequent-

ly read by the L7250 on the rising edges of SCLK (See Figure 2).

The microcontroller has to read (latch) the data on the falling edge of the SCLK signal. L7250 presents the data

on the SCLK rising edge. During a read mode the last address bit is latched by the L7250 on the eighth rising

edge of SCLK. The internal state machine then turns the SDATA bit around for the L7250 to assume control at

the next SCLK falling edge (the first falling edge after the 8th SCLK rising edge).

Symbol

Parameter

Min

Max

Unit

Tcc

Serial clock period

30

ns

Tch

Serial clock high time

13

ns

Tcl

Serial clock low time

13

ns

Tcds

Serial data setup time to clock falling edge (write mode)

5

ns

Tcdh

Serial clock falling edge to serial data hold time (write mode)

4

ns

Tedh

Serial clock falling edge to serial data hold time (read mode)

5

ns

Tcdd

Serial data setup time to clock falling edge (read mode)

5

ns

Tel

Serial Enable low time

490

ns

Teh

Serial Enable high time

30

ns

Tefcf

Serial Enable falling edge to serial clock falling edge

17

ns

Tcfer

Serial clock falling edge to Serial enable rising edge

17

ns

Tdly

SDATA turn around delay time

0

ns

Note 1: All specifications with respect to 50% of signal switching thresholds

Note 2: Reading mode tested at Max 20Mhz