L7250 datasheet(15/46 Pages) STMICROELECTRONICS

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L7250

1.4 Inverted clock serial port timing Table

Symbol

Parameter

Min

Max

Unit

Tcc

Serial clock period

Tch

Serial clock high time

Tcl

Serial clock low time

Tcds

Serial data setup time to clock falling edge (write mode)

Tcdh

Serial clock falling edge to serial data hold time (write mode)

Tedh

Serial clock falling edge to serial data hold time (read mode)

Tvld

Serial clock rising edge to SDATA stable time (read mode)

Cload=5pF (see Note2)

Cload=50pF (see Note2)

Tel

Serial Enable low time

490

Teh

Serial Enable high time

Tefcr

Serial Enable falling edge to serial clock rising edge

Tcrer

Serial clock rising edge to Serial enable rising edge

Tdly

SDATA turn around delay time

Note 1: All specifications with respect to 50% of signal switching thresholds

Note 2: In reading mode the clock frequency is limited by this parameter;

in fact the min ‘serial clock high time’ is defined by (Tvld+Tasu)

where Tasu = min ASIC setup time

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