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L7250

3.8.5 Constant Voltage Unload operation at POWER ON

The same costant voltage retract operation can be activated via software (during a power on phase). In that

case no actions are implemented to the spindle motor; the spindle motor will continue to mantain its running

status.

Again in power on condition if the bit ‘b3b2b1’ of the REG. 01H are set to 000 or 111 only one step costant volt-

age retract is activated as in power off condition with the difference that when the ‘End unload threshold’ is

reached the retract voltage is mantained applied to the motor until a different programmation is asserted via se-

rial port by the microcontroller.

In all the others ‘b3b2b1’ combination as the timer1 is elapsed the VCM is put in tristate condition.

NOTE: In case of Hard Disk application with CSS operation (no Ramp Loading), the polarity of the VCM connection must be re-

versed. In this way the active brake and the constant voltage unload operations will force the heads in the inner position

of the disks.

3.9 10 bit AD converter

The L7250 device includes a 10 bit analog to digital converter (hereafter ADC).

The ADC uses a two complement output code.

The ADC converts one of four different channels on demand, through SPI, and result of conversion can be read

from SPI too. The uC tells the ADC which channel must be converted, gives a start signal, reads the conversion

result; all this happens through the SPI.

The ADC convertion frequency, then its conversion time, could be changed using two bits into the serial port

(Reg 06H -> b1,b2). Setting these two bit to the configuration 00 the ADC can be disabled entering a sleep mode

status.

Hereafter is listed the recommended sequence of operations to obtain a conversion from ADC:

A)

µC selects which channel must be converted, writing the ADC_CH_ADDR field in SPI (Reg 0CH -> b1,b2);

µC selects the ADC input range writing the ADCRange bit (Reg 0CH -> b3);

µC writes high the ADC_START bit (Reg 0CH ->b0) in SPI (end of required conversion automatically resets it);

B) now

µC can read the conversion result from the SPI registers;

C) a new conversion can be required.

The

µC isn't allowed to require a conversion start when the ADC is already running; the start bit can be written

anyway, but ADC logic ignores it and continues the current conversion. If the uC avoids modifies over the

ADC_START bit, it can be used as a flag to state the end of the conversion.

The result of conversion is ten bits wide, larger than the 8 bits SPI registers, so it has been spanned over two

registers; if allowed by the precision required for the application, only the 8 msbits can be read with a single SPI

read operation, saving some time.

A new conversion can be required after the end of the previous one but before the read-back of the result, i.e.

swapping the order of (B) and (C) points listed before; working this way, it's possible to convert values closer in

time than with the previous sequence.

SPI includes an additional read-only field (2bits) that contains the channel number related to the present con-

version result.