MPF0900AMMA2ES datasheet(21/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

11.2.5 Self-test routine

In devices with a high safety integrity level (ASIL/SIL) the self-test routine is performed when the state machine

transitions out of the LPOFF state. During the self-test, the PF09 performs a startup self-check routine to verify

the integrity of the system:

The high speed oscillator circuit is operating within a maximum of 6 % tolerance.

The outputs of both the voltage generation bandgap and the monitoring bandgap are not drifting apart from

each other.

A CRC is performed on the mirror registers during the self-test routine, to ensure the integrity of the OTP

registers before powering up.

Analog built-in test on all voltage monitors and Safety I/Os is performed. (Refer to section Section 14.8 for

details on ABIST implementation.)

To allow for varying settling times for the internal bandgap and oscillators, the self-test routine is executed up

to three times (with 2 ms between each test) if a failure is encountered. If all three checks result in a failure, the

state machine will proceed to the Fail-safe transition to prevent operation with a potential latent fault present.

A failure in the ABIST test is not interpreted as a self-test failure, and it will only set the corresponding ABIST

flag in order to prevent the system from exiting a safe state after power-up.

11.2.6 Power-up sequence

The PF09 provides a highly configurable power-up sequence to enable the system regulators and general

purpose IO pins in a specific order and timing during the power-up state.

The default configuration for the power-up sequence is loaded from the OTP registers to ensure the system

always turns on with the correct configuration every power-up cycle as defined on each specific part number.

The RSTB pin is also programmable as part of the power-up sequence, and it is used as the condition to enter

the SYSTEM ON states.

Voltage monitoring functions are provided during the power-up sequence to ensure the system is brought out

of reset only if all voltage regulators enabled before the RSTB pin have reached regulation and are operating

properly.

The RSTB may be released in the middle of the Power-up sequence. In this case, the remaining supplies in

the power-up still continue to ramp up while the state machine enters the system-on states to process fault

conditions actively.

Refer to section Section 12.3.3 for details.

11.2.7 RUN State

If the power-up sequence is completed successfully, the state machine transitions directly into the RUN state.

The RUN State is a full-featured state providing full functionality and monitoring as described in this document.

All safety-related monitoring is fully operational during the RUN State if the corresponding feature is enabled via

OTP or functional registers.

Upon entering the RUN State, the I2C functional registers are loaded with the default values set by the OTP

registers, or with the default configuration. The MCU is expected to perform a booting sequence to modify the

PMIC functional configuration as required by the application.

All registers to control the regulators' output voltage, operating modes, interrupt masks and other miscellaneous

functions can be written to or read from the functional I2C register map during the SYSTEM ON states once the

power-up sequence is finalized.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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