MPF0900AMMA2ES datasheet(45/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

PD_SEQ_DLY[2:0]

Delay after power-down sequence

000

No delay

001

1 ms

010

5 ms

011

10 ms

100

50 ms

101

100 ms

110

250 ms

111

500 ms

Table 42. Delay after power-down sequence

The default value of the power-down delay is set via the OTP_PD_SEQ_DLY[2:0] bits, and the MCU can modify

the value during the SYSTEM ON states via the PD_SEQ_DLY[2:0] bits.

After a power-down sequence is started, the PWRON pin is masked until the power-down sequences are

finished and the programmable power-down delay is over. Only then can the device power up again if a power-

up event is present.

aaa-056052

SYSTEM ON

state

PWRON

Power-down sequence

Shutdown

event

VAON ON in LPOFF

VAON OFF

OFF state

Power-down

sequence

Power-down delay

Power down delay

System

regulators

VAON

RSTB

Figure 13. Power-down delay

12.5 RUN/STANDBY transitions

The PF09 provides independent configuration for the voltage regulators during the RUN and STANDBY states.

the PF09 relies on the power-up and power-down sequencing to ensure proper transition between these two

states.

Figure 14 shows an example of the Power-up/down sequence when transitioning from RUN to STANDBY and

back to the RUN state.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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