MPF0900AMMA2ES datasheet(95/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

The OTP_SW1_DVSMIN[3:0] bits are provided to define the maximum low voltage delta allowed during a DVS

transition. The maximum low-voltage delta is calculated with respect to the default voltage setting selected by

the OTP_VSW1_RUN[7:0] bits, to ensure the system is not able to request a voltage change outside of the

selected limits defined for a specific application.

OTP_SW1_DVSMIN[3:0]

SW1 low-voltage delta

0000

0.025 V

0001

0.050 V

0010

0.075 V

0011

0.100 V

0100

0.125 V

0101

0.150 V

0110

0.175 V

0111

0.200 V

1000

0.225 V

1001

0.250 V

1010

0.275 V

1011

0.300 V

1100

0.325 V

1101

0.350 V

1110

0.375 V

1111

0.400 V

Table 114. Minimum DVS selection bits

If the MCU tries to write a voltage value in SW1 lower than the OTP_SW1_DVSMIN[3:0] selection, the controller

will ignore the command and send a DVSMIN_I interrupt. The DVSMIN_I interrupt will assert the INTB pin if the

interrupt is not masked.

The SW1_RUN_MODE[1:0] bits are provided to change the mode of operation of the SW1 regulator during the

RUN state. If the SW1 is enabled in the Power-up sequence, the SW1_RUN_MODE[1:0] will be set to PWM by

default.

SW1_RUN_MODE[1:0]

Mode selection in RUN

OFF

PWM

PFM

Reserved

Table 115. Mode selection in RUN

The SW1_STBY_MODE[1:0] bits are provided to change the mode of operation of the SW1 regulators during

the STANDBY state.

SW1_STBY_MODE[1:0]

Mode selection in STANDBY

OFF

Table 116. Mode selection in STANDBY

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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