MPF0900AMMA2ES datasheet(39/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

When OTP_PWRON_MODE = 1, the device will start a power-down event when the PWRON pin sees a

transition from high to low and remains low for longer than TRESET And OTP_PWRON_RST_EN = 0

When VIN_OV_EN = 1 and VIN_OV_SDWN = 1, the device will start a power-down event when a VIN_OV

event is present.

The device will start a power-down event If the OTP_XFAILB_EN = 1 and the XFAILB pin is pulled low

externally.

When a PMIC OFF command is sent by writing SYS_CMD[7:0] = 0xA5, the device will start a 500 μs shutdown

timer.

When the shutdown timer is started, the device will trigger an SDWN_I interrupt and assert the INTB pin,

provided it is not masked. If the 500 μs timer is expired, the device will start a turn-off event. If the SDWN_I bit is

cleared before the 500 μs shutdown timer is expired, the shutdown request is stopped and the shutdown timer

is reset.

When the VAON is configured as an always-on regulator, the OTP_XFAILB_VAON bit is used to configure the

behavior of the VAON upon an external XFAILB event

OTP_XFAILB_VAON

VAON reaction on XFAILB

VAON not affected

VAON reset

Table 33. VAON reaction on XFAILB

When OTP_XFAILB_VAON = 0, the VAON will remain enabled while the device cycles through the LPOFF

State.

When OTP_XFAILB_VAON = 1, the VAON will be disabled at the end of the power down sequence, and

enabled again once the power-down delay is over and the device enters the LPOFF State.

12.4.1.2 Turn-off event due to a hard fault condition

The PF09 will start a power-down event when any of the following conditions are present:

• When an OV, UV or ILIM condition is present long enough for the fault timer to expire.

• When FAULT_CNT[3:0] = FAULT_MAX_CNT[3:0]

• When TJ is at least 10 °C below the TSD threshold

• When the reset counter reaches the maximum count (RESET_CNT = RESET_MAX)

• When the RSTB pin is shorted externally for longer than the OTP_RSTB_TSHORT[1:0] timer

12.4.2 Reset conditions

The PF09 will start a reset event when any of the following events are present:

• A watchdog failure

• A fault condition in the XRESET input (FCCU1 pin)

• A fault condition in the FCCU interface (if programmed to generate the reset)

• A fault condition in the ERRMON input (if programmed to generate the reset)

• A reset event can be initiated by the PWRON pin in Edge-sensitive mode and OTP_PWRON_RST_EN = 1

A software reset can be requested by writing SYS_CMD[7:0] = 0x3E

Reset events can be classified into two types:

1. Hard reset

2. Soft reset

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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