6.42

7133SA/LA, 7143SA/LA

High-Speed 2K x 16 Dual-Port RAM

Military, Industrial and Commercial Temperature Ranges

4

Jun.16.21

Pin Names

Left Port

Right Port

Names

CEL

CER

Chip Enable

R/WLUB

R/WRUB

Upper Byte Read/Write Enable

R/WLLB

R/WRLB

Lower Byte Read/Write Enable

OEL

OER

Output Enable

A0L - A10L

A0R - A10R

Address

I/O0L - I/O15L

I/O0R - I/O15R

Data Input/Output

BUSYL

BUSYR

Busy Flag

VCC

Power

GND

Ground

2746 tbl 01

Pin Configurations(1,2,3,4) (con't.)

NOTES:

1. Both VCC pins must be connected to the power supply to ensure reliable

operation.

2. Both GND pins must be connected to the ground supply to ensure reliable

operation.

3. PNG100 package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

7133/43

PNG100(4)

2746 drw 03

I/O9L

I/O8L

I/O7L

I/O6L

I/O5L

I/O4L

I/O3L

I/O2L

GND

I/O1L

I/O0L

OEL

VCC

R/

WLLB

CEL

R/

WLUB

N/C

N/C

N/C

A10L

A9L

A8L

A7L

A6L

I/O7R

I/O8R

I/O9R

I/O10R

I/O11R

I/O12R

I/O13R

I/O14R

GND

I/O15R

R/

WRLB

GND

N/C

N/C

A10R

A9R

A8R

A7R

A6R

A5R

N/C

N/C

N/C

OER

CER

R/

WRUB

100-Pin TQFP

Top View