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7133LA55G 数据表(PDF) 16 Page - Renesas Technology Corp

部件名 7133LA55G
功能描述  HIGH SPEED 2K X 16 DUAL-PORT SRAM
PDF  19 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

7133LA55G 数据表(HTML) 16 Page - Renesas Technology Corp

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6.42
7133SA/LA, 7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
16
Jun.16.21
Truth Table I – Non-Contention Read/Write Control(4)
Truth Table II — Address BUSY
Arbitration
NOTES:
1. Pins BUSYL and BUSYR are both outputs on the IDT7133 (MASTER). Both are
inputs on the IDT7143 (SLAVE). On Slaves the BUSY input internally inhibits
writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable
inputs of this port. “H” if the inputs to the opposite port became stable after the
address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR
= VIL will result BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level on
the pin.
NOTES:
1. A0L - A10L
≠A0R - A10R
2. If BUSY = LOW, data is not written.
3. If BUSY = LOW, data may not be valid, see tWDD and tDDD timing.
4. "H" = HIGH, "L" = LOW, "X" = Don’t Care, "Z" = High-Impedance, "LB" = Lower Byte, "UB" = Upper Byte
LEFT OR RIGHT PORT(1)
Function
R/WLB
R/WUB
CE
OE
I/O0-7
I/O8-15
X
X
H
X
Z
Z
Port Disabled and in Power Down Mode, ISB2, ISB4
XX
H
X
Z
Z
CER = CEL = VIH, Power Down Mode, ISB1 or ISB3
LLL
X
DATAIN
DATAIN
Data on Lower Byte and Upper Byte Written into Memory(2)
LH
L
L
DATAIN
DATAOUT
Data on Lower Byte Written into Memory(2), Data in Memory Output on
Upper Byte(3)
H
LLL
DATAOUT
DATAIN
Data in Memory Output on Lower Byte(3), Data on Upper Byte Written into
Memory(2)
LH
LH
DATAIN
Z
Data on Lower Byte Written into Memory(2)
HL
L
H
Z
DATAIN
Data on Upper Byte Written into Memory(2)
HH
L
L
DATAOUT
DATAOUT
Data in Memory Output on Lower Byte and Upper Byte
H
H
L
H
Z
Z
High Impedance Outputs
2746 tbl 13
Inputs
Outputs
Function
CEL
CER
A0L-A10L
A0R-A10R
BUSYL(1)
BUSYR(1)
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
2746 tbl 14



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