5/24

M28C64

Read

The device is accessed like a static RAM. When E

and G are low, and W is high, the contents of the

addressed location are presented on the I/O pins.

Otherwise, when either G or E is high, the I/O pins

revert to their high impedance state.

Write

Write operations are initiated when both W and E

are low and G is high. The device supports both

W-controlled and E-controlled write cycles (as

shown in Figure 11 and Figure 12). The address is

latched during the falling edge of W or E (which

ever occurs later) and the data is latched on the

rising edge of W or E (which ever occurs first).

the value specified in Table 10A to Table 10C, the

internal write cycle starts. It continues, under

internal timing control, until the write operation is

complete. The commencement of this period can

be detected by reading the Page Load Timer

Status on DQ5. The end of the cycle can be

detected by reading the status of the Data Polling

and the Toggle Bit functions on DQ7 and DQ6.

Page Write

The Page Write mode allows up to 64 bytes to be

written on a single page in a single go. This is

achieved through a series of successive Write

operations, no two of which are separated by more

to Table 10C).

All bytes must be located on the same page

address (A12-A6 must be the same for all bytes).

The internal write cycle can start at any instant

internally timed, and continues, uninterrupted,

until completion.

As with the single byte Write operation, described

above, the DQ5, DQ6 and DQ7 lines can be used

to detect the beginning and end of the internally

controlled phase of the Page Write cycle.

Software Data Protection (SDP)

The device offers a software-controlled write-

protection mechanism that allows the user to

inhibit all write operations to the device. This can

be useful

for protecting

the

memory

from

inadvertent write cycles that may occur during

periods of instability (uncontrolled bus conditions

when excessive noise is detected, or when power

supply levels are outside their specified values).

By

default,

the

device

is

shipped

in

the

“unprotected” state: the memory contents can be

freely changed by the user. Once the Software

Data Protection Mode is enabled, all write

commands are ignored, and have no effect on the

memory contents.

The device remains in this mode until a valid

Software Data Protection disable sequence is

received. The device reverts to its “unprotected”

state.

The status of the Software Data Protection

(enabled or disabled) is represented by a non-

Figure 4. Software Data Protection Enable Algorithm and Memory Write

Note: 1. The most significant address bits (A12 to A6) differ during these specific Page Write operations.

AI01356C

Write AAh in

Address 1555h

Write 55h in

Address 0AAAh

Write A0h in

Address 1555h

SDP is set

Write AAh in

Address 1555h

Write 55h in

Address 0AAAh

Write A0h in

Address 1555h

Page Write

(1 up to 64 bytes)

Write to Memory

When SDP is SET

SDP Enable Algorithm

Page Write

Timing

(see note 1)

Page Write

Timing

(see note 1)

Write

is enabled

Physical

Page Write

Instruction