M28C64 datasheet(6/24 Pages) STMICROELECTRONICS

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M28C64

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volatile latch, and is remembered across periods

of the power being off.

The Software Data Protection Enable command

consists of the writing of three specific data bytes

to three specific memory locations (each location

being on a different page), as shown in Figure 4.

Similarly to disable the Software Data Protection,

the user has to write specific data bytes into six

different locations, as shown in Figure 5. This

complex series of operations protects against the

chance of inadvertent enabling or disabling of the

Software Data Protection mechanism.

When SDP is enabled, the memory array can still

have data written to it, but the sequence is more

complex

(and

hence

better

protected

from

inadvertent use). The sequence is as shown in

Figure 4. This consists of an unlock key, to enable

the write action, at the end of which the SDP

continues to be enabled. This allows the SDP to

be enabled, and data to be written, within a single

Write cycle (tWC).

Software Chip Erase

Using this function, available on the M28C64 but

not on the M28C64-A or M28C64-xxW, the

contents of the entire memory are erased (set to

FFh) by holding Chip Enable (E) low, and holding

Output Enable (G) at VCC+7.0V. The chip is

cleared when a 10 ms low pulse is applied to the

Write Enable (W) signal (see Figure 7 and Table 5

for details).

Status Bits

The devices provide three status bits (DQ7, DQ6

and DQ5), and one output pin (RB), for use during

write operations. These allow the application to

use the write time latency of the device for getting

on with other work. These signals are available on

the I/O port bits DQ7, DQ6 and DQ5 (but only

during programming cycle, once a byte or more

has been latched into the memory) or continuously

on the RB output pin.

Data Polling bit (DQ7). The internally timed write

cycle starts after tWLQ5H (defined in Table 10A to

Table 10C) has elapsed since the previous byte

was latched in to the memory. The value of the

DQ7 bit of this last byte, is used as a signal

Figure 5. Software Data Protection Disable Algorithm

AI01357B

Write AAh in

Address 1555h

Write 55h in

Address 0AAAh

Write 80h in

Address 1555h

Unprotected State

Write AAh in

Address 1555h

Write 55h in

Address 0AAAh

Write 20h in

Address 1555h

Page Write

Timing

Figure 6. Status Bit Assignment

AI02815

PLTS

Hi-Z

PLTS

Hi-Z

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

= Data Polling

= Toggle Bit

= Page Load Timer Status

= High impedance

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