M48T35AY datasheet(2/19 Pages) STMICROELECTRONICS

2 / 19 page

M48T35AY, M48T35AV

2/19

Figure 2A. DIP Connections

DQ0

A13

A10

DQ7

A11

DQ5

DQ1

DQ2

DQ3

VSS

DQ4

DQ6

A12

A14

VCC

AI02798B

M48T35AY

M48T35AV

Figure 2B. SOIC Connections

AI02799

DQ0

A13

A10

DQ7

A11

DQ5

DQ1

DQ2

DQ3

VSS

DQ4

DQ6

A12

A14

VCC

M48T35AY

M48T35AV

completion of the surface mount process. Inser-

tion of the SNAPHAT housing after reflow pre-

vents potential battery and crystal damage due to

the high temperatures required for device surface-

mounting. The SNAPHAT housing is keyed to pre-

vent reverse insertion.

The SOIC and battery/crystal packages are

shipped separately in plastic anti-static tubes or in

Tape & Reel form.

For the 28 lead SOIC, the battery/crystal package

(i.e.

SNAPHAT)

part

number

"M4T28-

BR12SH1".

As Figure 3 shows, the static memory array and

the quartz controlled clock oscillator of the

M48T35AY/35AV are integrated on one silicon

chip. The two circuits are interconnected at the up-

per eight memory locations to provide user acces-

sible BYTEWIDE™ clock information in the bytes

with addresses 7FF8h-7FFFh.

The clock locations contain the year, month, date,

day, hour, minute, and second in 24 hour BCD for-

mat. Corrections for 28, 29 (leap year), 30, and 31

day months are made automatically. Byte 7FF8h

is the clock control register. This byte controls user

access to the clock information and also stores the

clock calibration setting.

Table 1. Signal Names

A0-A14

Address Inputs

DQ0-DQ7

Data Inputs / Outputs

Chip Enable

Output Enable

Write Enable

VCC

Supply Voltage

VSS

Ground

The 28 pin 600mil DIP CAPHAT™ houses the

M48T35AY/35AV silicon with a quartz crystal and

a long life lithium button cell in a single package.

The 28 pin 330mil SOIC provides sockets with

gold plated contacts at both ends for direct con-

nection to a separate SNAPHAT housing contain-

ing the battery and crystal. The unique design

allows the SNAPHAT battery package to be

mounted on top of the SOIC package after the

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