M48T59 datasheet(10/21 Pages) STMICROELECTRONICS

10 / 21 page

M48T59, M48T59Y, M48T59V

10/21

condition reset will not occur unless the addresses

are stable at the flag location for at least 15ns

while the divice is in the read mode as shown in

Figure 11.

The IRQ/FT pin is an open drain output and re-

quires a pull-up resistor (10k

Ω recommended) to

VCC. The pin remains in the high impedance state

unless an interrupt occurs or the frequency test

mode is enabled.

CLOCK OPERATIONS

Reading the Clock

Updates to the TIMEKEEPER registers should be

halted before clock data is read to prevent reading

data in transition. Because the BiPORT TIME-

KEEPER cells in the RAM array are only data reg-

isters, and not the actual clock counters, updating

the registers can be halted without disturbing the

clock itself.

Updating is halted when a ’1’ is written to the

READ bit, D6 in the Control register (1FF8h). As

long as a ’1’ remains in that position, updating is

halted.

After a halt is issued, the registers reflect the

count; that is, the day, date, and the time that were

current at the moment the halt command was is-

sued.

All of the TIMEKEEPER registers are updated si-

multaneously. A halt will not interrupt an update in

progress. Updating is within a second after the bit

is reset to a ’0’.

Setting the Clock

Bit D7 of the Control register (1FF8h) is the

WRITE bit. Setting the WRITE bit to a ’1’, like the

READ bit, halts updates to the TIMEKEEPER reg-

during the time the device is sampling VCC. There-

fore, decoupling of the power supply lines is rec-

ommended.

When VCC drops below VSO, the control circuit

switches power to the internal battery which pre-

serves data and powers the clock. The internal

button cell will maintain data in the M48T59/59Y/

59V for an accumulated period of at least 7 years

when VCC is less than VSO. As system power re-

turns and VCC rises above VSO, the battery is dis-

connected, and the power supply is switched to

external VCC. Deselect continues for tREC after

VCC reaches VPFD (max).

For more information on Battery Storage Life refer

to the Application Note AN1012.

POWER-ON RESET

The M48T59/59Y/59V continuously monitors VCC.

When VCC falls to the power fail detect trip point,

the RST pulls low (open drain) and remains low on

power-up for 40ms to 200ms after VCC passes

VPFD. RST is valid for all VCC conditions. The RST

pin is an open drain output and an appropriate re-

sistor to VCC should be chosen to control rise time.

PROGRAMMABLE INTERRUPTS

The M48T59/59Y/59V provides two programma-

ble interrupts; an alarm and a watchdog. When an

interrupt condition occurs, the M48T59/59Y/59V

sets the appropriate flag bit in the flag register

1FF0h. The interrupt enable bits in (AFE and ABE)

in 1FF6h and the Watchdog Steering (WDS) bit in

1FF7h allow the interrupt to activate the IRQ/FT

pin.

The interrupt flags and the IRQ/FT output are

cleared by a read to the flags register. An interrupt

Figure 9. Clock Calibration

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

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