Symbol

Parameter

M48Z2M1 / M48Z2M1Y

Unit

-70

Min

Max

Write Cycle Time

70

ns

Address Valid to Write Enable Low

0

ns

Address Valid to Chip Enable Low

0

ns

Write Enable Pulse Width

55

ns

Chip Enable Low to Chip Enable High

55

ns

Write Enable High to Address Transition

5

ns

Chip Enable High to Address Transition

15

ns

Input Valid to Write Enable High

30

ns

Input Valid to Chip Enable High

30

ns

Write Enable High to Input Transition

0

ns

Chip Enable High to Input Transition

10

ns

(1,2)

Write Enable Low to Output Hi-Z

25

ns

Address Valid to Write Enable High

65

ns

Address Valid to Chip Enable High

65

ns

(1,2)

Write Enable High to Output Transition

5

ns

2. If E goes low simultaneously with W going low, the outputs remain in the high-impedance state.

Table 10. Write Mode AC Characteristics

POWER SUPPLY DECOUPLING and UNDER-

SHOOT PROTECTION

switching, can produce voltage fluctuations, result-

be reduced if capacitors are used to store energy,

the bypass capacitors will be released as low going

spikes are generated or energy will be absorbed

when overshoots occur. A bypass capacitor value

of 0.1

µF (as shown in Figure 8) is recommended

in order to provide the needed filtering.

In addition to transients that are caused by normal

SRAM operation, power cycling can generate

negative spikes can cause data corruption in the

SRAM while in battery backup mode. To protect

from these voltage spikes, it is recommeded to

1N5817 is recommended for through hole and

MBRS120T3 is recommended for surface mount.

AI02169

VCC

0.1

µF

DEVICE

VCC

VSS

Figure 8. Supply Voltage Protection

8/12

M48Z2M1, M48Z2M1Y